Searched refs:core_dc (Results 1 – 12 of 12) sorted by relevance
275 struct dc *core_dc; in dc_stream_set_cursor_attributes() local293 core_dc = stream->ctx->dc; in dc_stream_set_cursor_attributes()294 res_ctx = &core_dc->current_state->res_ctx; in dc_stream_set_cursor_attributes()306 delay_cursor_until_vupdate(pipe_ctx, core_dc); in dc_stream_set_cursor_attributes()307 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true); in dc_stream_set_cursor_attributes()310 core_dc->hwss.set_cursor_attribute(pipe_ctx); in dc_stream_set_cursor_attributes()311 if (core_dc->hwss.set_cursor_sdr_white_level) in dc_stream_set_cursor_attributes()312 core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in dc_stream_set_cursor_attributes()316 core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false); in dc_stream_set_cursor_attributes()326 struct dc *core_dc; in dc_stream_set_cursor_position() local[all …]
115 struct dc *core_dc = dc; in dc_create_plane_state() local124 construct(core_dc->ctx, plane_state); in dc_create_plane_state()144 struct dc *core_dc; in dc_plane_get_status() local155 core_dc = plane_state->ctx->dc; in dc_plane_get_status()157 if (core_dc->current_state == NULL) in dc_plane_get_status()161 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()163 &core_dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()173 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()175 &core_dc->current_state->res_ctx.pipe_ctx[i]; in dc_plane_get_status()180 core_dc->hwss.update_pending_status(pipe_ctx); in dc_plane_get_status()
72 struct dc *core_dc = link->ctx->dc; in dp_enable_link_phy() local73 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dp_enable_link_phy()177 struct dc *core_dc = link->ctx->dc; in dp_disable_link_phy() local178 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dp_disable_link_phy()367 struct dc *core_dc = pipe_ctx->stream->ctx->dc; in dp_set_dsc_on_rx() local371 if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) in dp_set_dsc_on_rx()374 result = dm_helpers_dp_write_dsc_enable(core_dc->ctx, stream, enable); in dp_set_dsc_on_rx()384 struct dc *core_dc = pipe_ctx->stream->ctx->dc; in dp_set_dsc_on_stream() local420 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()445 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()[all …]
2320 struct dc *core_dc = link->ctx->dc; in dc_link_set_backlight_level() local2321 struct abm *abm = core_dc->res_pool->abm; in dc_link_set_backlight_level()2322 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dc_link_set_backlight_level()2340 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) { in dc_link_set_backlight_level()2341 if (core_dc->current_state->res_ctx. in dc_link_set_backlight_level()2348 core_dc->current_state-> in dc_link_set_backlight_level()2355 if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL) in dc_link_set_backlight_level()2373 struct dc *core_dc = link->ctx->dc; in dc_link_set_abm_disable() local2374 struct abm *abm = core_dc->res_pool->abm; in dc_link_set_abm_disable()2386 struct dc *core_dc = link->ctx->dc; in dc_link_set_psr_enable() local[all …]
313 struct dc *core_dc = dc; in context_timing_trace() local316 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index; in context_timing_trace()320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()332 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
2747 struct dc *core_dc = dc; in dc_validate_stream() local2749 struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; in dc_validate_stream()
75 struct dc *core_dc = clk_mgr_base->ctx->dc; in dce112_set_clock() local76 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_clock()113 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()129 struct dc *core_dc = clk_mgr->base.ctx->dc; in dce112_set_dispclk() local130 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_dispclk()155 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_dispclk()
91 struct dc *core_dc = clk_mgr->base.ctx->dc; in rv1_vbios_smu_set_dispclk() local92 struct dmcu *dmcu = core_dc->res_pool->dmcu; in rv1_vbios_smu_set_dispclk()103 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in rv1_vbios_smu_set_dispclk()
85 struct dc *core_dc = clk_mgr->base.ctx->dc; in rn_vbios_smu_set_dispclk() local86 struct dmcu *dmcu = core_dc->res_pool->dmcu; in rn_vbios_smu_set_dispclk()98 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in rn_vbios_smu_set_dispclk()
207 struct dc *core_dc = irq_service->ctx->dc; in dce110_vblank_set() local215 core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
293 struct dc *core_dc = clk_mgr->ctx->dc; in dce112_set_clock() local294 struct dmcu *dmcu = core_dc->res_pool->dmcu; in dce112_set_clock()329 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { in dce112_set_clock()
946 struct dc *core_dc; in dce110_enable_audio_stream() local954 core_dc = pipe_ctx->stream->ctx->dc; in dce110_enable_audio_stream()955 clk_mgr = core_dc->clk_mgr; in dce110_enable_audio_stream()960 if (core_dc->res_pool->pp_smu) in dce110_enable_audio_stream()961 pp_smu = core_dc->res_pool->pp_smu; in dce110_enable_audio_stream()966 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) in dce110_enable_audio_stream()
