Searched refs:clock_limits (Results 1 – 8 of 8) sorted by relevance
162 .clock_limits = {2545 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()2546 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()2568 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; in dcn20_calculate_wm()2569 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn20_calculate_wm()2574 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; in dcn20_calculate_wm()2575 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; in dcn20_calculate_wm()2585 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()2586 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; in dcn20_calculate_wm()2596 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; in dcn20_calculate_wm()[all …]
236 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()239 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()240 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()241 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()242 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()254 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()255 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()256 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()257 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()258 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()[all …]
111 struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; member
79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
159 .clock_limits = {959 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()960 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()1285 dcn2_1_soc.clock_limits[i].state = i; in update_bw_bounding_box()1286 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in update_bw_bounding_box()1287 dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in update_bw_bounding_box()1288 dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in update_bw_bounding_box()1290 dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; in update_bw_bounding_box()
1259 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1318 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1638 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
