Searched refs:clk_settle (Results 1 – 4 of 4) sorted by relevance
43 cfg->clk_settle = 95000; in phy_mipi_dphy_get_default_config()108 if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000) in phy_mipi_dphy_config_validate()
71 unsigned int clk_settle; member
308 s32 clk_settle; member
329 timing->clk_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A, in cio2_csi2_calc_timing()343 dev_dbg(dev, "freq cs value is %d\n", timing->clk_settle); in cio2_csi2_calc_timing()377 writel(timing.clk_settle, q->csi_rx_base + in cio2_hw_init()
