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Searched refs:clk_rate (Results 1 – 25 of 126) sorted by relevance

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/Linux-v5.4/drivers/memory/
Dti-aemif.c123 unsigned long clk_rate; member
179 unsigned long clk_rate = aemif->clk_rate; in aemif_config_abus() local
185 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); in aemif_config_abus()
186 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); in aemif_config_abus()
187 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); in aemif_config_abus()
188 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); in aemif_config_abus()
189 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); in aemif_config_abus()
190 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); in aemif_config_abus()
191 wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); in aemif_config_abus()
217 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) in aemif_cycles_to_nsec() argument
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/Linux-v5.4/drivers/clocksource/
Dtimer-oxnas-rps.c130 ulong clk_rate = clk_get_rate(rps->clk); in oxnas_rps_clockevent_init() local
135 rps->timer_period = DIV_ROUND_UP(clk_rate, HZ); in oxnas_rps_clockevent_init()
136 timer_rate = clk_rate; in oxnas_rps_clockevent_init()
140 timer_rate = clk_rate / 16; in oxnas_rps_clockevent_init()
145 timer_rate = clk_rate / 256; in oxnas_rps_clockevent_init()
167 clk_rate, in oxnas_rps_clockevent_init()
185 ulong clk_rate = clk_get_rate(rps->clk); in oxnas_rps_clocksource_init() local
189 clk_rate = clk_rate / 16; in oxnas_rps_clocksource_init()
197 TIMER_BITS, clk_rate); in oxnas_rps_clocksource_init()
200 clk_rate, 250, TIMER_BITS, in oxnas_rps_clocksource_init()
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Dtimer-vf-pit.c159 unsigned long clk_rate; in pit_timer_init() local
188 clk_rate = clk_get_rate(pit_clk); in pit_timer_init()
189 cycle_per_jiffy = clk_rate / (HZ); in pit_timer_init()
194 ret = pit_clocksource_init(clk_rate); in pit_timer_init()
198 return pit_clockevent_init(clk_rate, irq); in pit_timer_init()
/Linux-v5.4/drivers/watchdog/
Dloongson1_wdt.c23 unsigned long clk_rate; member
45 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat); in ls1x_wdt_set_timeout()
92 unsigned long clk_rate; in ls1x_wdt_probe() local
117 clk_rate = clk_get_rate(drvdata->clk); in ls1x_wdt_probe()
118 if (!clk_rate) in ls1x_wdt_probe()
120 drvdata->clk_rate = clk_rate; in ls1x_wdt_probe()
127 ls1x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000; in ls1x_wdt_probe()
Dimgpdc_wdt.c116 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); in __pdc_wdt_set_timeout() local
120 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; in __pdc_wdt_set_timeout()
188 unsigned long clk_rate; in pdc_wdt_probe() local
232 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); in pdc_wdt_probe()
233 if (clk_rate == 0) { in pdc_wdt_probe()
238 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { in pdc_wdt_probe()
243 if (order_base_2(clk_rate) == 0) in pdc_wdt_probe()
252 do_div(div, clk_rate); in pdc_wdt_probe()
Dtangox_wdt.c43 unsigned long clk_rate; member
60 ticks = 1 + wdt->timeout * dev->clk_rate; in tangox_wdt_start()
85 return (count - 1) / dev->clk_rate; in tangox_wdt_get_timeleft()
142 dev->clk_rate = clk_get_rate(dev->clk); in tangox_wdt_probe()
143 if (!dev->clk_rate) in tangox_wdt_probe()
151 dev->wdt.max_hw_heartbeat_ms = (U32_MAX - 1) / dev->clk_rate; in tangox_wdt_probe()
Dlantiq_wdt.c64 unsigned long clk_rate; member
103 timeout = wdt->timeout * priv->clk_rate; in ltq_wdt_start()
131 timeout = wdt->timeout * priv->clk_rate; in ltq_wdt_ping()
147 return do_div(timeout, priv->clk_rate); in ltq_wdt_get_timeleft()
219 priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER; in ltq_wdt_probe()
220 if (!priv->clk_rate) { in ltq_wdt_probe()
230 wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate; in ltq_wdt_probe()
Dorion_wdt.c76 unsigned long clk_rate; member
95 dev->clk_rate = clk_get_rate(dev->clk); in orion_wdt_clock_init()
118 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; in armada370_wdt_clock_init()
138 dev->clk_rate = clk_get_rate(dev->clk); in armada375_wdt_clock_init()
157 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; in armada375_wdt_clock_init()
181 dev->clk_rate = clk_get_rate(dev->clk); in armadaxp_wdt_clock_init()
189 writel(dev->clk_rate * wdt_dev->timeout, in orion_wdt_ping()
192 writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout), in orion_wdt_ping()
204 writel(dev->clk_rate * wdt_dev->timeout, in armada375_start()
207 writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout), in armada375_start()
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Dlpc18xx_wdt.c55 unsigned long clk_rate; member
107 val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate, in __lpc18xx_wdt_set_timeout()
129 return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; in lpc18xx_wdt_get_timeleft()
252 lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk); in lpc18xx_wdt_probe()
253 if (lpc18xx_wdt->clk_rate == 0) { in lpc18xx_wdt_probe()
262 LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate); in lpc18xx_wdt_probe()
265 LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; in lpc18xx_wdt_probe()
Drenesas_wdt.c36 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
39 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
51 unsigned long clk_rate; member
78 delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); in rwdt_wait_cycles()
215 priv->clk_rate = clk_get_rate(clk); in rwdt_probe()
220 if (!priv->clk_rate) { in rwdt_probe()
226 clks_per_sec = priv->clk_rate / clk_divs[i]; in rwdt_probe()
/Linux-v5.4/drivers/pwm/
Dpwm-omap-dmtimer.c48 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) in pwm_omap_dmtimer_get_clock_cycles() argument
50 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); in pwm_omap_dmtimer_get_clock_cycles()
100 unsigned long clk_rate; in pwm_omap_dmtimer_config() local
120 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
121 if (!clk_rate) { in pwm_omap_dmtimer_config()
126 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate); in pwm_omap_dmtimer_config()
144 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns); in pwm_omap_dmtimer_config()
145 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns); in pwm_omap_dmtimer_config()
150 period_ns, clk_rate); in pwm_omap_dmtimer_config()
157 duty_ns, clk_rate); in pwm_omap_dmtimer_config()
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Dpwm-lpss-pci.c19 .clk_rate = 25000000,
26 .clk_rate = 19200000,
33 .clk_rate = 19200000,
41 .clk_rate = 19200000,
Dpwm-rockchip.c66 unsigned long clk_rate; in rockchip_pwm_get_state() local
75 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
79 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
83 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
106 u64 clk_rate, div; in rockchip_pwm_config() local
109 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_config()
116 div = clk_rate * state->period; in rockchip_pwm_config()
120 div = clk_rate * state->duty_cycle; in rockchip_pwm_config()
Dpwm-sun4i.c110 u64 clk_rate, tmp; in sun4i_pwm_get_state() local
114 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
141 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
144 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
151 u64 clk_rate, div = 0; in sun4i_pwm_calculate() local
154 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_calculate()
165 div = clk_rate * state->period + NSEC_PER_SEC / 2; in sun4i_pwm_calculate()
177 div = clk_rate; in sun4i_pwm_calculate()
Dpwm-lpss-platform.c20 .clk_rate = 25000000,
27 .clk_rate = 19200000,
35 .clk_rate = 19200000,
Dpwm-rcar.c72 unsigned long clk_rate = clk_get_rate(rp->clk); in rcar_pwm_get_clock_division() local
75 if (clk_rate == 0) in rcar_pwm_get_clock_division()
79 tmp = (u64)period_ns * clk_rate + div - 1; in rcar_pwm_get_clock_division()
107 unsigned long clk_rate = clk_get_rate(rp->clk); in rcar_pwm_set_counter() local
111 do_div(one_cycle, clk_rate); in rcar_pwm_set_counter()
/Linux-v5.4/drivers/mfd/
Dintel-lpss-acpi.c22 .clk_rate = 120000000,
31 .clk_rate = 120000000,
43 .clk_rate = 120000000,
49 .clk_rate = 100000000,
60 .clk_rate = 133000000,
72 .clk_rate = 133000000,
/Linux-v5.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_core_perf.c260 u64 clk_rate = kms->perf.perf_tune.min_core_clk; in _dpu_core_perf_get_core_clk_rate() local
267 clk_rate = max(dpu_cstate->new_perf.core_clk_rate, in _dpu_core_perf_get_core_clk_rate()
268 clk_rate); in _dpu_core_perf_get_core_clk_rate()
269 clk_rate = clk_round_rate(kms->perf.core_clk->clk, in _dpu_core_perf_get_core_clk_rate()
270 clk_rate); in _dpu_core_perf_get_core_clk_rate()
275 clk_rate = kms->perf.fix_core_clk_rate; in _dpu_core_perf_get_core_clk_rate()
277 DPU_DEBUG("clk:%llu\n", clk_rate); in _dpu_core_perf_get_core_clk_rate()
279 return clk_rate; in _dpu_core_perf_get_core_clk_rate()
287 u64 clk_rate = 0; in dpu_core_perf_crtc_update() local
367 clk_rate = _dpu_core_perf_get_core_clk_rate(kms); in dpu_core_perf_crtc_update()
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/Linux-v5.4/arch/m68k/include/asm/
Dmcfclk.h33 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \ argument
37 .rate = clk_rate, \
44 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \ argument
47 .rate = clk_rate, \
/Linux-v5.4/drivers/nvmem/
Dimx-ocotp.c172 unsigned long clk_rate = 0; in imx_ocotp_set_imx6_timing() local
204 clk_rate = clk_get_rate(priv->clk); in imx_ocotp_set_imx6_timing()
206 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; in imx_ocotp_set_imx6_timing()
207 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS, in imx_ocotp_set_imx6_timing()
210 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US, in imx_ocotp_set_imx6_timing()
224 unsigned long clk_rate = 0; in imx_ocotp_set_imx7_timing() local
231 clk_rate = clk_get_rate(priv->clk); in imx_ocotp_set_imx7_timing()
232 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, in imx_ocotp_set_imx7_timing()
234 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, in imx_ocotp_set_imx7_timing()
Dvf610-ocotp.c116 u32 clk_rate; in vf610_ocotp_calculate_timing() local
120 clk_rate = clk_get_rate(ocotp_dev->clk); in vf610_ocotp_calculate_timing()
123 relax = clk_rate / (1000000000 / DEF_RELAX) - 1; in vf610_ocotp_calculate_timing()
124 strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; in vf610_ocotp_calculate_timing()
125 strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; in vf610_ocotp_calculate_timing()
Dlpc18xx_eeprom.c167 unsigned long clk_rate; in lpc18xx_eeprom_probe() local
217 clk_rate = clk_get_rate(eeprom->clk); in lpc18xx_eeprom_probe()
218 clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1; in lpc18xx_eeprom_probe()
219 lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate); in lpc18xx_eeprom_probe()
/Linux-v5.4/drivers/phy/st/
Dphy-stm32-usbphyc.c86 static void stm32_usbphyc_get_pll_params(u32 clk_rate, in stm32_usbphyc_get_pll_params() argument
104 do_div(ndiv, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
108 do_div(frac, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
116 u32 clk_rate = clk_get_rate(usbphyc->clk); in stm32_usbphyc_pll_init() local
120 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) || in stm32_usbphyc_pll_init()
121 (clk_rate > PLL_INFF_MAX_RATE_HZ)) { in stm32_usbphyc_pll_init()
123 clk_rate); in stm32_usbphyc_pll_init()
127 stm32_usbphyc_get_pll_params(clk_rate, &pll_params); in stm32_usbphyc_pll_init()
139 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll), in stm32_usbphyc_pll_init()
/Linux-v5.4/drivers/usb/phy/
Dphy-generic.c213 u32 clk_rate = 0; in usb_phy_gen_create_phy() local
219 if (of_property_read_u32(node, "clock-frequency", &clk_rate)) in usb_phy_gen_create_phy()
220 clk_rate = 0; in usb_phy_gen_create_phy()
235 clk_rate = pdata->clk_rate; in usb_phy_gen_create_phy()
270 if (!IS_ERR(nop->clk) && clk_rate) { in usb_phy_gen_create_phy()
271 err = clk_set_rate(nop->clk, clk_rate); in usb_phy_gen_create_phy()
/Linux-v5.4/sound/soc/atmel/
Dmchp-i2s-mcc.c398 unsigned long clk_rate; in mchp_i2s_mcc_config_divs() local
421 for (clk_rate = lcm_rate; in mchp_i2s_mcc_config_divs()
422 (clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) && in mchp_i2s_mcc_config_divs()
423 (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0)); in mchp_i2s_mcc_config_divs()
424 clk_rate += lcm_rate) { in mchp_i2s_mcc_config_divs()
425 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate, in mchp_i2s_mcc_config_divs()
430 clk_rate, ret); in mchp_i2s_mcc_config_divs()
434 clk_rate); in mchp_i2s_mcc_config_divs()
439 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate, in mchp_i2s_mcc_config_divs()
444 clk_rate, ret); in mchp_i2s_mcc_config_divs()
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