Searched refs:clk_pll1 (Results 1 – 7 of 7) sorted by relevance
| /Linux-v5.4/arch/arm/mach-ep93xx/ |
| D | clock.c | 71 static struct clk clk_pll1 = { variable
75 .parent = &clk_pll1,
78 .parent = &clk_pll1,
81 .parent = &clk_pll1,
214 INIT_CK(NULL, "pll1", &clk_pll1),
367 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()
383 mclk = &clk_pll1; in calc_clk_div()
549 clk_pll1.rate = clk_xtali.rate; in ep93xx_clock_init()
551 clk_pll1.rate = calc_pll_rate(value); in ep93xx_clock_init()
554 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; in ep93xx_clock_init()
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| /Linux-v5.4/drivers/gpu/drm/sun4i/ |
| D | sun8i_hdmi_phy.c | 669 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1"); in sun8i_hdmi_phy_probe()
670 if (IS_ERR(phy->clk_pll1)) { in sun8i_hdmi_phy_probe()
672 ret = PTR_ERR(phy->clk_pll1); in sun8i_hdmi_phy_probe()
727 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_probe()
751 clk_put(phy->clk_pll1); in sun8i_hdmi_phy_remove()
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| D | sun8i_hdmi_phy_clk.c | 155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
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| D | sun8i_dw_hdmi.h | 171 struct clk *clk_pll1; member
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| /Linux-v5.4/drivers/clk/sirf/ |
| D | clk-common.c | 217 static struct clk_pll clk_pll1 = { variable
413 if (rate == clk_get_rate(clk_pll1.hw.clk)) { in cpu_clk_set_rate()
414 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
431 if (cur_parent == clk_pll1.hw.clk) { in cpu_clk_set_rate()
436 ret2 = clk_set_rate(clk_pll1.hw.clk, rate); in cpu_clk_set_rate()
438 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
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| D | clk-atlas6.c | 71 &clk_pll1.hw,
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| D | clk-prima2.c | 70 &clk_pll1.hw,
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