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Searched refs:clk_id (Results 1 – 25 of 248) sorted by relevance

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/Linux-v5.4/drivers/clk/zynqmp/
Dpll.c20 u32 clk_id; member
49 u32 clk_id = clk->clk_id; in zynqmp_pll_get_mode() local
55 ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0, in zynqmp_pll_get_mode()
72 u32 clk_id = clk->clk_id; in zynqmp_pll_set_mode() local
83 ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL); in zynqmp_pll_set_mode()
136 u32 clk_id = clk->clk_id; in zynqmp_pll_recalc_rate() local
144 ret = eemi_ops->clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
151 eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0, in zynqmp_pll_recalc_rate()
175 u32 clk_id = clk->clk_id; in zynqmp_pll_set_rate() local
190 ret = eemi_ops->clock_setdivider(clk_id, m); in zynqmp_pll_set_rate()
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Dclk-gate-zynqmp.c23 u32 clk_id; member
38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable() local
42 ret = eemi_ops->clock_enable(clk_id); in zynqmp_clk_gate_enable()
59 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable() local
63 ret = eemi_ops->clock_disable(clk_id); in zynqmp_clk_gate_disable()
80 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled() local
84 ret = eemi_ops->clock_getstate(clk_id, &state); in zynqmp_clk_gate_is_enabled()
110 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, in zynqmp_clk_register_gate() argument
134 gate->clk_id = clk_id; in zynqmp_clk_register_gate()
Dclkc.c78 u32 clk_id; member
120 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
145 static inline int zynqmp_is_valid_clock(u32 clk_id) in zynqmp_is_valid_clock() argument
147 if (clk_id >= clock_max_idx) in zynqmp_is_valid_clock()
150 return clock[clk_id].valid; in zynqmp_is_valid_clock()
160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
164 ret = zynqmp_is_valid_clock(clk_id); in zynqmp_get_clock_name()
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
180 static int zynqmp_get_clock_type(u32 clk_id, u32 *type) in zynqmp_get_clock_type() argument
184 ret = zynqmp_is_valid_clock(clk_id); in zynqmp_get_clock_type()
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Dclk-mux-zynqmp.c32 u32 clk_id; member
47 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_get_parent() local
52 ret = eemi_ops->clock_getparent(clk_id, &val); in zynqmp_clk_mux_get_parent()
72 u32 clk_id = mux->clk_id; in zynqmp_clk_mux_set_parent() local
76 ret = eemi_ops->clock_setparent(clk_id, index); in zynqmp_clk_mux_set_parent()
106 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, in zynqmp_clk_register_mux() argument
130 mux->clk_id = clk_id; in zynqmp_clk_register_mux()
Ddivider.c42 u32 clk_id; member
64 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate() local
70 ret = eemi_ops->clock_getdivider(clk_id, &div); in zynqmp_clk_divider_recalc_rate()
105 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate() local
113 ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); in zynqmp_clk_divider_round_rate()
148 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_set_rate() local
163 ret = eemi_ops->clock_setdivider(clk_id, div); in zynqmp_clk_divider_set_rate()
189 u32 clk_id, in zynqmp_clk_register_divider() argument
215 div->clk_id = clk_id; in zynqmp_clk_register_divider()
Dclk-zynqmp.h35 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
40 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
46 u32 clk_id,
51 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
57 u32 clk_id,
/Linux-v5.4/drivers/clk/keystone/
Dsci-clk.c61 u32 clk_id; member
84 clk->clk_id, enable_ssc, in sci_clk_prepare()
101 clk->clk_id); in sci_clk_unprepare()
105 clk->dev_id, clk->clk_id, ret); in sci_clk_unprepare()
122 clk->clk_id, &req_state, in sci_clk_is_prepared()
127 clk->dev_id, clk->clk_id, ret); in sci_clk_is_prepared()
150 clk->clk_id, &freq); in sci_clk_recalc_rate()
154 clk->dev_id, clk->clk_id, ret); in sci_clk_recalc_rate()
180 clk->clk_id, in sci_clk_determine_rate()
188 clk->dev_id, clk->clk_id, ret); in sci_clk_determine_rate()
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/Linux-v5.4/drivers/soc/mediatek/
Dmtk-scpsys.c81 enum clk_id { enum
118 enum clk_id clk_id[MAX_CLKS]; member
418 for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { in init_scp()
419 struct clk *c = clk[data->clk_id[j]]; in init_scp()
485 .clk_id = {CLK_NONE},
493 .clk_id = {CLK_MM},
503 .clk_id = {CLK_MFG},
512 .clk_id = {CLK_MM},
521 .clk_id = {CLK_MM},
529 .clk_id = {CLK_NONE},
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/Linux-v5.4/drivers/firmware/arm_scmi/
Dclock.c99 u32 clk_id, struct scmi_clock_info *clk) in scmi_clock_attributes_get() argument
106 sizeof(clk_id), sizeof(*attr), &t); in scmi_clock_attributes_get()
110 put_unaligned_le32(clk_id, t->tx.buf); in scmi_clock_attributes_get()
124 scmi_clock_describe_rates_get(const struct scmi_handle *handle, u32 clk_id, in scmi_clock_describe_rates_get() argument
145 clk_desc->id = cpu_to_le32(clk_id); in scmi_clock_describe_rates_get()
197 scmi_clock_rate_get(const struct scmi_handle *handle, u32 clk_id, u64 *value) in scmi_clock_rate_get() argument
207 put_unaligned_le32(clk_id, t->tx.buf); in scmi_clock_rate_get()
217 static int scmi_clock_rate_set(const struct scmi_handle *handle, u32 clk_id, in scmi_clock_rate_set() argument
237 cfg->id = cpu_to_le32(clk_id); in scmi_clock_rate_set()
254 scmi_clock_config_set(const struct scmi_handle *handle, u32 clk_id, u32 config) in scmi_clock_config_set() argument
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/Linux-v5.4/sound/soc/ti/
Domap-dmic.c278 static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id, in omap_dmic_select_fclk() argument
297 if (dmic->sysclk == clk_id) { in omap_dmic_select_fclk()
308 switch (clk_id) { in omap_dmic_select_fclk()
319 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); in omap_dmic_select_fclk()
352 dmic->sysclk = clk_id; in omap_dmic_select_fclk()
362 static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id, in omap_dmic_select_outclk() argument
367 if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) { in omap_dmic_select_outclk()
369 clk_id); in omap_dmic_select_outclk()
389 static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, in omap_dmic_set_dai_sysclk() argument
395 return omap_dmic_select_fclk(dmic, clk_id, freq); in omap_dmic_set_dai_sysclk()
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Domap-abe-twl6040.c52 int clk_id, freq; in omap_abe_hw_params() local
55 clk_id = twl6040_get_clk_id(codec_dai->component); in omap_abe_hw_params()
56 if (clk_id == TWL6040_SYSCLK_SEL_HPPLL) in omap_abe_hw_params()
58 else if (clk_id == TWL6040_SYSCLK_SEL_LPPLL) in omap_abe_hw_params()
64 ret = snd_soc_dai_set_sysclk(codec_dai, clk_id, freq, in omap_abe_hw_params()
/Linux-v5.4/drivers/clk/tegra/
Dclk-tegra-audio.c35 int clk_id; member
41 .clk_id = tegra_clk_ ## _name,\
66 int clk_id; member
77 .clk_id = tegra_clk_ ## _name ## _2x,\
181 dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks); in tegra_audio_clk_init()
207 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in tegra_audio_clk_init()
231 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in tegra_audio_clk_init()
Dclk.c231 for (; dup_list->clk_id < clk_max; dup_list++) { in tegra_init_dup_clks()
232 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
243 for (; tbl->clk_id < clk_max; tbl++) { in tegra_init_from_table()
244 clk = clks[tbl->clk_id]; in tegra_init_from_table()
247 __func__, PTR_ERR(clk), tbl->clk_id); in tegra_init_from_table()
340 struct clk ** __init tegra_lookup_dt_id(int clk_id, in tegra_lookup_dt_id() argument
343 if (tegra_clk[clk_id].present) in tegra_lookup_dt_id()
344 return &clks[tegra_clk[clk_id].dt_id]; in tegra_lookup_dt_id()
/Linux-v5.4/drivers/firmware/
Dti_sci.c958 u32 dev_id, u32 clk_id, in ti_sci_set_clock_state() argument
986 if (clk_id < 255) { in ti_sci_set_clock_state()
987 req->clk_id = clk_id; in ti_sci_set_clock_state()
989 req->clk_id = 255; in ti_sci_set_clock_state()
990 req->clk_id_32 = clk_id; in ti_sci_set_clock_state()
1023 u32 dev_id, u32 clk_id, in ti_sci_cmd_get_clock_state() argument
1054 if (clk_id < 255) { in ti_sci_cmd_get_clock_state()
1055 req->clk_id = clk_id; in ti_sci_cmd_get_clock_state()
1057 req->clk_id = 255; in ti_sci_cmd_get_clock_state()
1058 req->clk_id_32 = clk_id; in ti_sci_cmd_get_clock_state()
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Dti_sci.h273 u8 clk_id; member
299 u8 clk_id; member
342 u8 clk_id; member
364 u8 clk_id; member
402 u8 clk_id; member
453 u8 clk_id; member
512 u8 clk_id; member
533 u8 clk_id; member
/Linux-v5.4/sound/soc/codecs/
Dadav80x.c537 int clk_id, int source, in adav80x_set_sysclk() argument
544 switch (clk_id) { in adav80x_set_sysclk()
557 if (adav80x->clk_src != clk_id) { in adav80x_set_sysclk()
560 adav80x->clk_src = clk_id; in adav80x_set_sysclk()
561 if (clk_id == ADAV80X_CLK_XTAL) in adav80x_set_sysclk()
562 clk_id = ADAV80X_CLK_XIN; in adav80x_set_sysclk()
564 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) | in adav80x_set_sysclk()
565 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) | in adav80x_set_sysclk()
566 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); in adav80x_set_sysclk()
567 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); in adav80x_set_sysclk()
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Dmc13783.c242 int clk_id, unsigned int freq, int dir, in mc13783_set_sysclk() argument
260 if (clk_id == MC13783_CLK_CLIB) in mc13783_set_sysclk()
271 int clk_id, unsigned int freq, int dir) in mc13783_set_sysclk_dac() argument
273 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC); in mc13783_set_sysclk_dac()
277 int clk_id, unsigned int freq, int dir) in mc13783_set_sysclk_codec() argument
279 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC); in mc13783_set_sysclk_codec()
283 int clk_id, unsigned int freq, int dir) in mc13783_set_sysclk_sync() argument
287 ret = mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC); in mc13783_set_sysclk_sync()
291 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC); in mc13783_set_sysclk_sync()
Dtas2552.c393 static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, in tas2552_set_dai_sysclk() argument
400 switch (clk_id) { in tas2552_set_dai_sysclk()
407 clk_id = TAS2552_PLL_CLKIN_BCLK; in tas2552_set_dai_sysclk()
414 val = (clk_id << 3) & mask; /* bit 4:5 in the register */ in tas2552_set_dai_sysclk()
416 tas2552->pll_clk_id = clk_id; in tas2552_set_dai_sysclk()
424 val = (clk_id >> 1) & mask; /* bit 0:1 in the register */ in tas2552_set_dai_sysclk()
426 tas2552->pdm_clk_id = clk_id; in tas2552_set_dai_sysclk()
430 dev_err(component->dev, "Invalid clk id: %d\n", clk_id); in tas2552_set_dai_sysclk()
/Linux-v5.4/drivers/base/regmap/
Dregmap-mmio.c212 const char *clk_id, in regmap_mmio_gen_context() argument
299 if (clk_id == NULL) in regmap_mmio_gen_context()
302 ctx->clk = clk_get(dev, clk_id); in regmap_mmio_gen_context()
322 struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id, in __regmap_init_mmio_clk() argument
330 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config); in __regmap_init_mmio_clk()
340 const char *clk_id, in __devm_regmap_init_mmio_clk() argument
348 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config); in __devm_regmap_init_mmio_clk()
/Linux-v5.4/include/linux/
Dscmi_protocol.h70 (const struct scmi_handle *handle, u32 clk_id);
71 int (*rate_get)(const struct scmi_handle *handle, u32 clk_id,
73 int (*rate_set)(const struct scmi_handle *handle, u32 clk_id,
75 int (*enable)(const struct scmi_handle *handle, u32 clk_id);
76 int (*disable)(const struct scmi_handle *handle, u32 clk_id);
/Linux-v5.4/tools/testing/selftests/seccomp/
Dseccomp_benchmark.c19 unsigned long long timing(clockid_t clk_id, unsigned long long samples) in timing() argument
26 assert(clock_gettime(clk_id, &start) == 0); in timing()
31 assert(clock_gettime(clk_id, &finish) == 0); in timing()
/Linux-v5.4/arch/nds32/kernel/vdso/
Dgettimeofday.c196 register clockid_t clk_id asm("$r0") = _clk_id; in clock_getres_fallback()
203 :"r"(clk_id), "r"(res), "i"(__NR_clock_getres) in clock_getres_fallback()
209 notrace int __vdso_clock_getres(clockid_t clk_id, struct timespec *res) in __vdso_clock_getres() argument
215 switch (clk_id) { in __vdso_clock_getres()
228 return clock_getres_fallback(clk_id, res); in __vdso_clock_getres()
/Linux-v5.4/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c165 u8 clk_id; member
174 .clk_id = CLK_SRC_ ##_id, \
200 u8 clk_id; member
208 .clk_id = BASE_ ##_id ##_CLK, \
263 u8 clk_id; member
274 .clk_id = CLK_SRC_ ##_id, \
538 const char *name = clk_src_names[clk->clk_id]; in lpc18xx_cgu_register_div()
558 const char *name = clk_base_names[clk->clk_id]; in lpc18xx_register_base_clk()
585 const char *name = clk_src_names[clk->clk_id]; in lpc18xx_cgu_register_pll()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/
Damdgpu_smu.c162 int ret = 0, clk_id = 0; in smu_set_soft_freq_range() local
171 clk_id = smu_clk_get_index(smu, clk_type); in smu_set_soft_freq_range()
172 if (clk_id < 0) in smu_set_soft_freq_range()
173 return clk_id; in smu_set_soft_freq_range()
176 param = (uint32_t)((clk_id << 16) | (max & 0xffff)); in smu_set_soft_freq_range()
184 param = (uint32_t)((clk_id << 16) | (min & 0xffff)); in smu_set_soft_freq_range()
198 int ret = 0, clk_id = 0; in smu_set_hard_freq_range() local
207 clk_id = smu_clk_get_index(smu, clk_type); in smu_set_hard_freq_range()
208 if (clk_id < 0) in smu_set_hard_freq_range()
209 return clk_id; in smu_set_hard_freq_range()
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Dsmu_v11_0.c586 input.clk_id = SMU11_SYSPLL0_SOCCLK_ID; in smu_v11_0_get_clk_info_from_vbios()
600 input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID; in smu_v11_0_get_clk_info_from_vbios()
614 input.clk_id = SMU11_SYSPLL0_ECLK_ID; in smu_v11_0_get_clk_info_from_vbios()
628 input.clk_id = SMU11_SYSPLL0_VCLK_ID; in smu_v11_0_get_clk_info_from_vbios()
642 input.clk_id = SMU11_SYSPLL0_DCLK_ID; in smu_v11_0_get_clk_info_from_vbios()
658 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID; in smu_v11_0_get_clk_info_from_vbios()
946 int clk_id; in smu_v11_0_get_max_sustainable_clock() local
955 clk_id = smu_clk_get_index(smu, clock_select); in smu_v11_0_get_max_sustainable_clock()
956 if (clk_id < 0) in smu_v11_0_get_max_sustainable_clock()
960 clk_id << 16); in smu_v11_0_get_max_sustainable_clock()
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