Searched refs:clk_cfg (Results 1 – 7 of 7) sorted by relevance
223 unsigned int clk_cfg; in ep93xx_i2s_set_dai_fmt() local227 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG); in ep93xx_i2s_set_dai_fmt()231 clk_cfg |= EP93XX_I2S_CLKCFG_REL; in ep93xx_i2s_set_dai_fmt()235 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; in ep93xx_i2s_set_dai_fmt()239 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; in ep93xx_i2s_set_dai_fmt()251 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER; in ep93xx_i2s_set_dai_fmt()256 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER; in ep93xx_i2s_set_dai_fmt()266 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS); in ep93xx_i2s_set_dai_fmt()271 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP; in ep93xx_i2s_set_dai_fmt()272 clk_cfg |= EP93XX_I2S_CLKCFG_LRS; in ep93xx_i2s_set_dai_fmt()[all …]
109 u32 val, clk_div, clk_cfg; in xlnx_spdif_hw_params() local117 clk_cfg = 0; in xlnx_spdif_hw_params()120 clk_cfg = 1; in xlnx_spdif_hw_params()123 clk_cfg = 2; in xlnx_spdif_hw_params()126 clk_cfg = 3; in xlnx_spdif_hw_params()129 clk_cfg = 4; in xlnx_spdif_hw_params()132 clk_cfg = 5; in xlnx_spdif_hw_params()135 clk_cfg = 6; in xlnx_spdif_hw_params()143 val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT; in xlnx_spdif_hw_params()
199 u8 clk_cfg, reg; in bcm63xx_spi_setup_transfer() local203 clk_cfg = SPI_CLK_0_391MHZ; in bcm63xx_spi_setup_transfer()208 clk_cfg = bcm63xx_spi_freq_table[i][1]; in bcm63xx_spi_setup_transfer()216 reg |= clk_cfg; in bcm63xx_spi_setup_transfer()220 clk_cfg, t->speed_hz); in bcm63xx_spi_setup_transfer()
601 u32 clk_cfg; in rp2_reset_asic() local609 clk_cfg = readw(base + RP2_ASIC_CFG); in rp2_reset_asic()610 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9); in rp2_reset_asic()611 writew(clk_cfg, base + RP2_ASIC_CFG); in rp2_reset_asic()
63 int clk_cfg; member1008 const struct cs35l36_pll_config *clk_cfg; in cs35l36_component_set_sysclk() local1034 clk_cfg = cs35l36_get_clk_config(cs35l36, freq); in cs35l36_component_set_sysclk()1035 if (clk_cfg == NULL) { in cs35l36_component_set_sysclk()1045 clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT); in cs35l36_component_set_sysclk()1074 clk_cfg->fll_igain); in cs35l36_component_set_sysclk()
405 u8 clk_cfg; member460 return cs35l35_clk_ctl[i].clk_cfg; in cs35l35_get_clk_config()
46 static struct ath10k_clk_info clk_cfg[] = { variable1535 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) { in ath10k_snoc_clk_init()1583 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) { in ath10k_snoc_clk_deinit()1705 ar_snoc->clk = clk_cfg; in ath10k_snoc_probe()1706 for (i = 0; i < ARRAY_SIZE(clk_cfg); i++) { in ath10k_snoc_probe()
