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Searched refs:clear_state_gpu_addr (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c136 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
275 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
Damdgpu_rlc.h140 uint64_t clear_state_gpu_addr; member
Dgfx_v6_0.c2408 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2418 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2830 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2937 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2945 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
Dgfx_v10_0.c968 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
1007 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v10_0_csb_vram_pin()
1792 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
1794 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
Dgfx_v7_0.c3887 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3888 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4538 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
Dgfx_v8_0.c1335 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v8_0_csb_vram_pin()
2112 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
3922 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3924 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
Dgfx_v9_0.c1694 adev->gfx.rlc.clear_state_gpu_addr = in gfx_v9_0_csb_vram_pin()
2606 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2608 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
/Linux-v5.4/drivers/gpu/drm/radeon/
Devergreen.c4267 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4286 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4293 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4413 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
Dsi.c5289 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5786 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5792 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
Dradeon.h994 uint64_t clear_state_gpu_addr; member
Dcik.c6633 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6634 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()