Searched refs:cl72_ctrl (Results 1 – 1 of 1) sorted by relevance
3728 u16 lane, i, cl72_ctrl, an_adv = 0, val; in bnx2x_warpcore_enable_AN_KR() local3748 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); in bnx2x_warpcore_enable_AN_KR()3749 cl72_ctrl &= 0x08ff; in bnx2x_warpcore_enable_AN_KR()3750 cl72_ctrl |= 0x3800; in bnx2x_warpcore_enable_AN_KR()3752 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); in bnx2x_warpcore_enable_AN_KR()
