Searched refs:cfgcr2 (Results 1 – 4 of 4) sorted by relevance
954 i915_reg_t ctl, cfgcr1, cfgcr2; member968 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),974 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),980 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),1010 I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2); in skl_ddi_pll_enable()1012 POSTING_READ(regs[id].cfgcr2); in skl_ddi_pll_enable()1072 hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()1363 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local1382 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | in skl_ddi_hdmi_pll_dividers()1393 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_hdmi_pll_dividers()[all …]
188 u32 cfgcr1, cfgcr2; member
1279 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_calc_wrpll_link()1280 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_calc_wrpll_link()1282 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_calc_wrpll_link()1283 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; in skl_calc_wrpll_link()
12803 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); in intel_pipe_config_compare()
