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Searched refs:cfgcr1 (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c954 i915_reg_t ctl, cfgcr1, cfgcr2; member
967 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
973 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
979 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1009 I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1011 POSTING_READ(regs[id].cfgcr1); in skl_ddi_pll_enable()
1071 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1363 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1378 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | in skl_ddi_hdmi_pll_dividers()
1392 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
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Dintel_dpll_mgr.h188 u32 cfgcr1, cfgcr2; member
Dintel_ddi.c1318 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) in skl_calc_wrpll_link()
1321 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) in skl_calc_wrpll_link()
1335 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in cnl_calc_wrpll_link()
1336 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in cnl_calc_wrpll_link()
1338 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in cnl_calc_wrpll_link()
1339 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in cnl_calc_wrpll_link()
Dintel_display.c12802 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_debugfs.c2846 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()