Searched refs:cfgcr0 (Results 1 – 5 of 5) sorted by relevance
2038 val = pll->state.hw_state.cfgcr0; in cnl_ddi_pll_enable()2046 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_pll_enable()2156 hw_state->cfgcr0 = val; in cnl_ddi_pll_get_hw_state()2320 u32 cfgcr0, cfgcr1; in cnl_ddi_hdmi_pll_dividers() local2323 cfgcr0 = DPLL_CFGCR0_HDMI_MODE; in cnl_ddi_hdmi_pll_dividers()2328 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) | in cnl_ddi_hdmi_pll_dividers()2340 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; in cnl_ddi_hdmi_pll_dividers()2348 u32 cfgcr0; in cnl_ddi_dp_set_dpll_hw_state() local2350 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE; in cnl_ddi_dp_set_dpll_hw_state()2354 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810; in cnl_ddi_dp_set_dpll_hw_state()[all …]
191 u32 cfgcr0; member
1374 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) in cnl_calc_wrpll_link()1377 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in cnl_calc_wrpll_link()1518 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_clock_get()1521 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; in cnl_ddi_clock_get()
12804 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
2845 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
