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Searched refs:ccm_base (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/clk/imx/
Dclk-vf610.c13 #define CCM_CCR (ccm_base + 0x00)
14 #define CCM_CSR (ccm_base + 0x04)
15 #define CCM_CCSR (ccm_base + 0x08)
16 #define CCM_CACRR (ccm_base + 0x0c)
17 #define CCM_CSCMR1 (ccm_base + 0x10)
18 #define CCM_CSCDR1 (ccm_base + 0x14)
19 #define CCM_CSCDR2 (ccm_base + 0x18)
20 #define CCM_CSCDR3 (ccm_base + 0x1c)
21 #define CCM_CSCMR2 (ccm_base + 0x20)
22 #define CCM_CSCDR4 (ccm_base + 0x24)
[all …]
Dclk-imx5.c30 #define MXC_CCM_CCR (ccm_base + 0x00)
31 #define MXC_CCM_CCDR (ccm_base + 0x04)
32 #define MXC_CCM_CSR (ccm_base + 0x08)
33 #define MXC_CCM_CCSR (ccm_base + 0x0c)
34 #define MXC_CCM_CACRR (ccm_base + 0x10)
35 #define MXC_CCM_CBCDR (ccm_base + 0x14)
36 #define MXC_CCM_CBCMR (ccm_base + 0x18)
37 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
38 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
39 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)
[all …]
Dclk.c25 void __init imx_mmdc_mask_handshake(void __iomem *ccm_base, in imx_mmdc_mask_handshake() argument
30 reg = readl_relaxed(ccm_base + CCM_CCDR); in imx_mmdc_mask_handshake()
32 writel_relaxed(reg, ccm_base + CCM_CCDR); in imx_mmdc_mask_handshake()
Dclk-imx6sl.c100 static void __iomem *ccm_base; variable
127 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
168 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()
169 writel_relaxed(arm_div_for_wait, ccm_base + CACRR); in imx6sl_set_wait_clk()
171 writel_relaxed(saved_arm_div, ccm_base + CACRR); in imx6sl_set_wait_clk()
173 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) in imx6sl_set_wait_clk()
296 ccm_base = base; in imx6sl_clocks_init()
Dclk-imx6q.c272 static void mmdc_ch1_disable(void __iomem *ccm_base) in mmdc_ch1_disable() argument
280 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_disable()
282 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_disable()
285 static void mmdc_ch1_reenable(void __iomem *ccm_base) in mmdc_ch1_reenable() argument
290 reg = readl_relaxed(ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
292 writel_relaxed(reg, ccm_base + CCM_CCSR); in mmdc_ch1_reenable()
324 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) in init_ldb_clks() argument
330 reg = readl_relaxed(ccm_base + CCM_CS2CDR); in init_ldb_clks()
372 mmdc_ch1_disable(ccm_base); in init_ldb_clks()
375 reg = readl_relaxed(ccm_base + CCM_CS2CDR); in init_ldb_clks()
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Dclk-imx25.c41 #define ccm(x) (ccm_base + (x))
86 static int __init __mx25_clocks_init(void __iomem *ccm_base) in __mx25_clocks_init() argument
88 BUG_ON(!ccm_base); in __mx25_clocks_init()
Dclk.h13 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
/Linux-v5.4/arch/arm/mach-imx/
Dpm-imx6.c61 static void __iomem *ccm_base; variable
224 struct imx6_pm_base ccm_base; member
233 u32 val = readl_relaxed(ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
238 writel_relaxed(val, ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
252 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
255 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
258 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
261 writel(val, ccm_base + CCR); in imx6_enable_rbc()
279 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()
282 writel_relaxed(val, ccm_base + CLPCR); in imx6q_enable_wb()
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Dpm-imx5.c133 static void __iomem *ccm_base; variable
152 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()
194 imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); in mx5_cpu_lp_set()
386 ccm_base = ioremap(data->ccm_addr, SZ_16K); in imx5_pm_common_init()
389 WARN_ON(!ccm_base || !cortex_base || !gpc_base); in imx5_pm_common_init()