Searched refs:cchip (Results 1 – 3 of 3) sorted by relevance
63 register titan_cchip *cchip = TITAN_cchip; in titan_update_irq_hw() local84 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()85 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()86 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()87 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()104 dimB = &cchip->dim0.csr; in titan_update_irq_hw()105 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()106 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()107 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
50 register tsunami_cchip *cchip = TSUNAMI_cchip; in tsunami_update_irq_hw() local69 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()70 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()71 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()72 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()89 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()90 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()91 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()92 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()
51 `-- cchip-specific files
