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/Linux-v5.4/Documentation/block/
Dwriteback_cache_control.rst9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
/Linux-v5.4/arch/arm/boot/compressed/
Dhead-xscale.S28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
/Linux-v5.4/arch/arm/mm/
Dproc-arm720.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
Dproc-sa110.S49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
Dproc-fa526.S39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm926.S53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mov r0, #4 @ disable write-back on caches explicitly
Dproc-sa1100.S57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm920.S61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
389 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-mohawk.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
359 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
Dproc-arm740.S40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
Dproc-arm925.S84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
436 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
443 mov r0, #4 @ disable write-back on caches explicitly
Dproc-arm1020e.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
415 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1022.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
408 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1026.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm922.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
380 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-xsc3.S92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
430 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
450 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
Dproc-arm1020.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-feroceon.S75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
520 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
533 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-xscale.S128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
547 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
561 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
/Linux-v5.4/arch/openrisc/
DKconfig81 bool "Have write through data caches"
84 Select this if your implementation features write through data caches.
86 caches at relevant times. Most OpenRISC implementations support write-
87 through data caches.
/Linux-v5.4/drivers/acpi/hmat/
Dhmat.c53 struct list_head caches; member
122 INIT_LIST_HEAD(&target->caches); in alloc_memory_target()
381 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()
606 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()
680 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()
/Linux-v5.4/Documentation/filesystems/nfs/
Drpc-cache.txt8 a wide variety of values to be caches.
10 There are a number of caches that are similar in structure though
12 of common code for managing these caches.
14 Examples of caches that are likely to be needed are:
92 includes it on a list of caches that will be regularly
/Linux-v5.4/tools/perf/util/
Denv.h67 struct cpu_cache_level *caches; member
Dheader.c1092 static int build_caches(struct cpu_cache_level caches[], u32 size, u32 *cntp) in build_caches() argument
1118 if (cpu_cache_level__cmp(&c, &caches[i])) in build_caches()
1123 caches[cnt++] = c; in build_caches()
1142 struct cpu_cache_level caches[max_caches]; in write_cache() local
1146 ret = build_caches(caches, max_caches, &cnt); in write_cache()
1150 qsort(&caches, cnt, sizeof(struct cpu_cache_level), cpu_cache_level__sort); in write_cache()
1161 struct cpu_cache_level *c = &caches[i]; in write_cache()
1187 cpu_cache_level__free(&caches[i]); in write_cache()
1773 cpu_cache_level__fprintf(fp, &ff->ph->env.caches[i]); in print_cache()
2531 struct cpu_cache_level *caches; in process_cache() local
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/Linux-v5.4/tools/testing/selftests/zram/
DREADME9 use as swap disks, various caches under /var and maybe many more :)

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