| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr_clk.c | 52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk… in rv1_dump_clk_registers() argument
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
59 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4) in rv1_dump_clk_registers()
60 bypass->dcfclk_bypass = 0; in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
70 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4) in rv1_dump_clk_registers()
71 bypass->dispclk_pypass = 0; in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
76 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4) in rv1_dump_clk_registers()
77 bypass->dprefclk_bypass = 0; in rv1_dump_clk_registers()
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| /Linux-v5.4/drivers/regulator/ |
| D | anatop-regulator.c | 30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
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| /Linux-v5.4/sound/soc/codecs/ |
| D | rl6231.c | 145 bool bypass = false; in rl6231_pll_calc() local
156 bypass = pll_preset_table[i].m_bp; in rl6231_pll_calc()
179 bypass = true; in rl6231_pll_calc()
187 bypass = true; in rl6231_pll_calc()
199 bypass = false; in rl6231_pll_calc()
214 pll_code->m_bp = bypass; in rl6231_pll_calc()
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| /Linux-v5.4/include/trace/events/ |
| D | bcache.h | 124 TP_PROTO(struct bio *bio, bool hit, bool bypass),
125 TP_ARGS(bio, hit, bypass),
133 __field(bool, bypass )
142 __entry->bypass = bypass;
148 __entry->nr_sector, __entry->cache_hit, __entry->bypass)
153 bool writeback, bool bypass),
154 TP_ARGS(c, inode, bio, writeback, bypass),
163 __field(bool, bypass )
173 __entry->bypass = bypass;
179 __entry->nr_sector, __entry->writeback, __entry->bypass)
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| /Linux-v5.4/arch/arm/mach-omap2/ |
| D | sram.h | 13 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
26 int bypass);
39 int bypass);
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| D | clkt2xxx_dpllcore.c | 113 u32 bypass = 0; in omap2_reprogram_dpllcore() local
161 bypass = 1; in omap2_reprogram_dpllcore()
168 bypass); in omap2_reprogram_dpllcore()
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| D | sram.c | 159 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
161 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) in omap2_set_prcm() argument
164 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); in omap2_set_prcm()
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| D | clkt2xxx_virt_prcm_set.c | 98 u32 cur_rate, done_rate, bypass = 0; in omap2_select_table_rate() local
133 bypass = 1; in omap2_select_table_rate()
151 bypass); in omap2_select_table_rate()
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| /Linux-v5.4/drivers/md/bcache/ |
| D | stats.c | 185 bool hit, bool bypass) in mark_cache_stats() argument
187 if (!bypass) in mark_cache_stats()
200 bool hit, bool bypass) in bch_mark_cache_accounting() argument
204 mark_cache_stats(&dc->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
205 mark_cache_stats(&c->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
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| D | request.c | 204 if (op->bypass) in bch_data_insert_start()
283 op->bypass = true; in bch_data_insert_start()
325 op->writeback, op->bypass); in bch_data_insert()
870 !s->cache_missed, s->iop.bypass); in cached_dev_read_done_bh()
871 trace_bcache_read(s->orig_bio, !s->cache_missed, s->iop.bypass); in cached_dev_read_done_bh()
891 if (s->cache_miss || s->iop.bypass) { in cached_dev_cache_miss()
991 s->iop.bypass = false; in cached_dev_write()
1003 s->iop.bypass = true; in cached_dev_write()
1007 s->iop.bypass)) { in cached_dev_write()
1008 s->iop.bypass = false; in cached_dev_write()
[all …]
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| /Linux-v5.4/drivers/clk/imx/ |
| D | clk-sccg-pll.c | 74 int bypass; member
149 temp_setup->bypass = PLL_BYPASS1; in clk_sccg_divq_lookup()
224 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sccg_divf1_lookup()
286 setup->bypass = PLL_BYPASS2; in clk_sccg_pll_find_setup()
377 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sccg_pll_set_rate()
414 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sccg_pll_set_parent()
425 int bypass) in __clk_sccg_pll_determine_rate() argument
436 switch (bypass) { in __clk_sccg_pll_determine_rate()
452 rate, bypass); in __clk_sccg_pll_determine_rate()
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| /Linux-v5.4/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
37 ti,c64x+pll-bypass-delay = <200>;
|
| /Linux-v5.4/net/sched/ |
| D | sch_fifo.c | 57 bool bypass; in fifo_init() local
77 bypass = sch->limit >= psched_mtu(qdisc_dev(sch)); in fifo_init()
79 bypass = sch->limit >= 1; in fifo_init()
81 if (bypass) in fifo_init()
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| /Linux-v5.4/Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 7 (reference clock and bypass clock), with digital phase locked
38 and second entry bypass clock
52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
68 ti,low-power-bypass;
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| D | fapll.txt | 7 (reference clock and bypass clock), and one or more child
15 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
| /Linux-v5.4/drivers/clk/at91/ |
| D | sckc.c | 122 bool bypass, in at91_clk_register_slow_osc() argument
148 if (bypass) in at91_clk_register_slow_osc()
374 bool bypass; in at91sam9x5_sckc_register() local
394 bypass = of_property_read_bool(child, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
398 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
405 xtal_name, 1200000, bypass, bits); in at91sam9x5_sckc_register()
468 bool bypass; in of_sam9x60_sckc_setup() local
483 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_sam9x60_sckc_setup()
485 xtal_name, 5000000, bypass, in of_sam9x60_sckc_setup()
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| D | sama5d4.c | 126 bool bypass; in sama5d4_pmc_setup() local
154 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d4_pmc_setup()
157 bypass); in sama5d4_pmc_setup()
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| /Linux-v5.4/Documentation/ABI/testing/ |
| D | sysfs-bus-i2c-devices-bq32k | 5 Description: Attribute for enable/disable the trickle charge bypass
7 enable/disable the Trickle charge FET bypass.
|
| /Linux-v5.4/drivers/clk/socfpga/ |
| D | clk-pll.c | 44 unsigned long bypass; in clk_pll_recalc_rate() local
47 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); in clk_pll_recalc_rate()
48 if (bypass & MAINPLL_BYPASS) in clk_pll_recalc_rate()
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| /Linux-v5.4/arch/mips/include/asm/octeon/ |
| D | cvmx-asxx-defs.h | 200 uint64_t bypass:1; member
202 uint64_t bypass:1;
469 uint64_t bypass:1; member
475 uint64_t bypass:1;
493 uint64_t bypass:1; member
503 uint64_t bypass:1;
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| /Linux-v5.4/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-jtag.c | 66 jtgc.s.bypass = 0x3; in cvmx_helper_qlm_jtag_init()
68 jtgc.s.bypass = 0xf; in cvmx_helper_qlm_jtag_init()
|
| /Linux-v5.4/Documentation/networking/ |
| D | nf_flowtable.txt | 16 output netdevice via neigh_xmit(), hence, they bypass the classic forwarding
32 including the Netfilter hooks and the flowtable fastpath bypass.
60 |__yes_________________fastpath bypass ____________________________|
74 Enabling the flowtable bypass is relatively easy, you only need to create a
99 forwarding bypass.
|
| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 869 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in skl_get_cdclk()
1022 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in skl_set_cdclk()
1099 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1157 cdclk_state.cdclk = cdclk_state.bypass; in skl_uninit_cdclk()
1197 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_de_pll_vco()
1222 if (cdclk == dev_priv->cdclk.hw.bypass) in glk_de_pll_vco()
1266 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in bxt_get_cdclk()
1347 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in bxt_set_cdclk()
1428 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in bxt_sanitize_cdclk()
1501 cdclk_state.cdclk = cdclk_state.bypass; in bxt_uninit_cdclk()
[all …]
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| /Linux-v5.4/arch/c6x/platforms/ |
| D | pll.c | 268 u8 bypass; in clk_pllclk_recalc() local
279 bypass = 0; in clk_pllclk_recalc()
281 bypass = 1; in clk_pllclk_recalc()
302 if (!bypass) { in clk_pllclk_recalc()
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| /Linux-v5.4/drivers/base/regmap/ |
| D | regcache.c | 344 bool bypass; in regcache_sync() local
350 bypass = map->cache_bypass; in regcache_sync()
384 map->cache_bypass = bypass; in regcache_sync()
413 bool bypass; in regcache_sync_region() local
420 bypass = map->cache_bypass; in regcache_sync_region()
439 map->cache_bypass = bypass; in regcache_sync_region()
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