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Searched refs:bit_idx (Results 1 – 25 of 90) sorted by relevance

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/Linux-v5.4/drivers/clk/
Dclk-gate.c70 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
72 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
77 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
79 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
111 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
113 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
139 void __iomem *reg, u8 bit_idx, in clk_hw_register_gate() argument
148 if (bit_idx > 15) { in clk_hw_register_gate()
167 gate->bit_idx = bit_idx; in clk_hw_register_gate()
185 void __iomem *reg, u8 bit_idx, in clk_register_gate() argument
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Dclk-stm32f4.c49 u8 bit_idx; member
414 u8 bit_idx; member
424 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
436 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
468 unsigned long flags, u8 bit_idx) in clk_register_apb_mul() argument
478 am->bit_idx = bit_idx; in clk_register_apb_mul()
543 u8 bit_idx; member
815 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
821 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
963 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, in clk_register_rgate() argument
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Dclk-stm32h7.c217 void __iomem *reg, u8 bit_idx, u8 bit_rdy, in clk_register_ready_gate() argument
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate() argument
342 gate->bit_idx = bit_idx; in _get_cgate()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
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Dclk-asm9260.c75 u8 bit_idx; member
302 base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); in asm9260_acc_init()
321 gd->bit_idx, 0, &asm9260_clk_lock); in asm9260_acc_init()
/Linux-v5.4/drivers/clk/imx/
Dclk-gate2.c30 u8 bit_idx; member
51 reg &= ~(3 << gate->bit_idx); in clk_gate2_enable()
52 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
77 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable()
84 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) in clk_gate2_reg_is_enabled() argument
88 if (((val >> bit_idx) & 1) == 1) in clk_gate2_reg_is_enabled()
98 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); in clk_gate2_is_enabled()
111 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable_unused()
127 void __iomem *reg, u8 bit_idx, u8 cgr_val, in clk_hw_register_gate2() argument
142 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
Dclk-lpcg-scu.c34 u8 bit_idx; member
49 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
55 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
72 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_disable()
85 u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu() argument
97 clk->bit_idx = bit_idx; in imx_clk_lpcg_scu()
/Linux-v5.4/drivers/xen/events/
Devents_2l.c168 int word_idx, bit_idx; in evtchn_2l_handle_events() local
178 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
179 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) in evtchn_2l_handle_events()
205 bit_idx = 0; in evtchn_2l_handle_events()
211 bit_idx = 0; /* usually scan entire word from start */ in evtchn_2l_handle_events()
226 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
233 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
239 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
242 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
248 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
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/Linux-v5.4/drivers/clk/hisilicon/
Dclkgate-separated.c27 u8 bit_idx; /* bits in enable/disable register */ member
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
58 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
72 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
86 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
104 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
/Linux-v5.4/drivers/clk/actions/
Dowl-gate.c27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
Dowl-gate.h18 u8 bit_idx; member
30 .bit_idx = _bit_idx, \
Dowl-pll.c119 return !!(reg & BIT(pll_hw->bit_idx)); in owl_pll_is_enabled()
130 reg |= BIT(pll_hw->bit_idx); in owl_pll_set()
132 reg &= ~BIT(pll_hw->bit_idx); in owl_pll_set()
Dowl-pll.h27 u8 bit_idx; member
46 .bit_idx = _bit_idx, \
/Linux-v5.4/drivers/clk/meson/
Dmeson8b.c281 .bit_idx = 27,
316 .bit_idx = 28,
344 .bit_idx = 29,
372 .bit_idx = 30,
400 .bit_idx = 31,
465 .bit_idx = 14,
510 .bit_idx = 14,
555 .bit_idx = 14,
612 .bit_idx = 7,
794 .bit_idx = 8,
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Dgxbb.c571 .bit_idx = 27,
598 .bit_idx = 28,
636 .bit_idx = 29,
662 .bit_idx = 30,
688 .bit_idx = 31,
746 .bit_idx = 14,
789 .bit_idx = 14,
832 .bit_idx = 14,
894 .bit_idx = 7,
945 .bit_idx = 8,
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Dg12a-aoclk.c47 .bit_idx = (_bit), \
79 .bit_idx = 14,
106 .bit_idx = 31,
179 .bit_idx = 30,
197 .bit_idx = 31,
270 .bit_idx = 30,
358 .bit_idx = 8,
Daxg-aoclk.c38 .bit_idx = (_bit), \
62 .bit_idx = 14,
77 .bit_idx = 31,
160 .bit_idx = 30,
248 .bit_idx = 8,
Dg12a.c219 .bit_idx = 24,
236 .bit_idx = 24,
292 .bit_idx = 24,
318 .bit_idx = 20,
1122 .bit_idx = 1,
1141 .bit_idx = 1,
1201 .bit_idx = 1,
1235 .bit_idx = 17,
1269 .bit_idx = 18,
1313 .bit_idx = 23,
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Daxg.c337 .bit_idx = 27,
364 .bit_idx = 28,
402 .bit_idx = 29,
428 .bit_idx = 30,
456 .bit_idx = 31,
522 .bit_idx = 14,
573 .bit_idx = 14,
629 .bit_idx = 14,
680 .bit_idx = 0,
830 .bit_idx = 4,
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Dclk-regmap.c18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
40 val ^= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
42 val &= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
Dgxbb-aoclk.c27 .bit_idx = (_bit), \
50 .bit_idx = 6,
65 .bit_idx = 31,
144 .bit_idx = 30,
Dclk-regmap.h43 u8 bit_idx; member
118 .bit_idx = (_bit), \
/Linux-v5.4/drivers/clk/mvebu/
Dcp110-system-controller.c116 u8 bit_idx; member
126 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
136 BIT(gate->bit_idx), 0); in cp110_gate_disable()
146 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
157 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
176 gate->bit_idx = bit_idx; in cp110_register_gate()
/Linux-v5.4/drivers/clk/ti/
Dinterface.c37 struct clk_omap_reg *reg, u8 bit_idx, in _register_interface() argument
51 clk_hw->enable_bit = bit_idx; in _register_interface()
/Linux-v5.4/drivers/clk/st/
Dclk-flexgen.c164 reg &= ~BIT(config->bit_idx); in flexgen_set_rate()
233 fgxbar->pgate.bit_idx = xbar_shift + 6; in clk_register_flexgen()
243 fgxbar->fgate.bit_idx = 6; in clk_register_flexgen()
253 fgxbar->sync.bit_idx = 7; in clk_register_flexgen()
/Linux-v5.4/drivers/clk/berlin/
Dcommon.h14 u8 bit_idx; member

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