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Searched refs:assigned (Results 1 – 25 of 645) sorted by relevance

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/Linux-v5.4/arch/arm/boot/dts/
Dimx7ulp.dtsi161 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
162 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
163 assigned-clock-rates = <24000000>;
173 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
174 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
175 assigned-clock-rates = <48000000>;
182 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
183 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
233 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
234 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
[all …]
Dexynos5422-odroidxu3-audio.dtsi32 assigned-clocks = <&clock CLK_MOUT_EPLL>,
41 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
47 assigned-clock-rates = <0>,
66 assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
68 assigned-clock-rates = <(196608000 / 256)>,
87 assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
88 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
Dexynos5422-odroidxu4.dts38 assigned-clocks = <&clock CLK_MOUT_EPLL>,
47 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
53 assigned-clock-rates = <0>,
73 assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
75 assigned-clock-rates = <(196608000 / 256)>,
81 assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
82 assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
Dexynos4412-odroid-common.dtsi144 assigned-clocks = <&clock CLK_FOUT_EPLL>;
145 assigned-clock-rates = <45158401>;
149 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
155 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
158 assigned-clock-rates = <0>, <0>,
202 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
204 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
205 assigned-clock-rates = <0>, <176000000>;
210 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
212 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
Dimx7d-pico.dtsi75 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_CKIL>;
78 assigned-clock-rates = <0>, <32768>;
91 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
93 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
94 assigned-clock-rates = <0>, <100000000>;
236 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
238 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
239 assigned-clock-rates = <0>, <24576000>;
269 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
Dimx7d-cl-som-imx7.dts43 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
45 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
46 assigned-clock-rates = <0>, <100000000>;
71 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
73 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
74 assigned-clock-rates = <0>, <100000000>;
193 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
194 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
208 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
209 assigned-clock-rates = <400000000>;
Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
Dimx7s-warp.dts84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
Dexynos4412-itop-elite.dts130 assigned-clocks = <&clock CLK_MOUT_CAM0>;
131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
135 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
141 assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
159 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
162 assigned-clock-rates = <0>, <176000000>;
Dimx7d-nitrogen7.dts114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
116 assigned-clock-parents = <&clks IMX7D_CKIL>;
117 assigned-clock-rates = <0>, <32768>;
127 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
129 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
130 assigned-clock-rates = <0>, <100000000>;
318 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
319 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
326 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
327 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
Dexynos4210-trats.dts208 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
210 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
211 assigned-clock-rates = <0>, <160000000>;
216 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
218 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
219 assigned-clock-rates = <0>, <160000000>;
224 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
226 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
227 assigned-clock-rates = <0>, <160000000>;
232 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
[all …]
Dstih407.dtsi16 assigned-clocks = <&clk_s_d2_quadfs 0>,
28 assigned-clock-parents = <0>,
40 assigned-clock-rates = <297000000>,
88 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
95 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/Linux-v5.4/arch/mips/boot/dts/img/
Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/display/msm/
Ddpu.txt38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
40 the assigned-clocks property.
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
72 the assigned-clocks property.
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88 assigned-clock-rates = <300000000>;
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
118 assigned-clock-rates = <0 0 300000000 19200000>;
/Linux-v5.4/arch/mips/boot/dts/ingenic/
Dgcw0.dts50 assigned-clocks =
53 assigned-clock-parents =
56 assigned-clock-rates =
67 assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
68 assigned-clock-rates = <750000>, <750000>;
/Linux-v5.4/drivers/staging/wilc1000/
Dmicrochip,wilc1000,spi.txt13 - rtc_clk : Clock connected on the rtc clock line. Must be assigned
14 a frequency with assigned-clocks property, and must be
30 assigned-clocks = <&pck1>;
31 assigned-clock-rates = <32768>;
Dmicrochip,wilc1000,sdio.txt13 - rtc_clk : Clock connected on the rtc clock line. Must be assigned
14 a frequency with assigned-clocks property, and must be
31 assigned-clocks = <&pck1>;
32 assigned-clock-rates = <32768>;
/Linux-v5.4/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.txt25 - assigned-clocks: reference to the rtc_ck clock entry.
26 - assigned-clock-parents: phandle of the new parent clock of rtc_ck.
34 assigned-clocks = <&rcc 1 CLK_RTC>;
35 assigned-clock-parents = <&rcc 1 CLK_LSE>;
46 assigned-clocks = <&rcc RTC_CK>;
47 assigned-clock-parents = <&rcc LSE_CK>;
/Linux-v5.4/drivers/s390/char/
Dsclp_cmd.c241 u16 assigned; member
264 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
425 static void __init insert_increment(u16 rn, int standby, int assigned) in insert_increment() argument
439 if (assigned && incr->rn > rn) in insert_increment()
441 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
446 if (!assigned) in insert_increment()
478 int i, id, assigned, rc; in sclp_detect_standby_memory() local
488 assigned = 0; in sclp_detect_standby_memory()
498 for (i = 0; i < sccb->assigned; i++) { in sclp_detect_standby_memory()
501 assigned++; in sclp_detect_standby_memory()
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;
/Linux-v5.4/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
14 - assigned-clock-parents: parent of mux clock.
30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
/Linux-v5.4/Documentation/devicetree/bindings/pwm/
Dpwm-sprd.txt16 - assigned-clocks: Reference to the PWM clock entries.
17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
31 assigned-clocks = <&aon_clk CLK_PWM0>,
35 assigned-clock-parents = <&ext_26m>,
/Linux-v5.4/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt22 - assigned-clocks : Shall be:
25 - assigned-clock-rates : Shall be:
43 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
44 assigned-clock-rates = <100000000>, <100000000>;

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