Home
last modified time | relevance | path

Searched refs:arm_v7s_cfg (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/iommu/
Dmsm_iommu.c281 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr); in __program_context()
282 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]); in __program_context()
283 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]); in __program_context()
286 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr); in __program_context()
287 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr); in __program_context()
Dio-pgtable-arm-v7s.c802 cfg->arm_v7s_cfg.tcr = ARM_V7S_TCR_PD1; in arm_v7s_alloc_pgtable()
809 cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) | in arm_v7s_alloc_pgtable()
814 cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) | in arm_v7s_alloc_pgtable()
826 cfg->arm_v7s_cfg.ttbr[0] = virt_to_phys(data->pgd) | in arm_v7s_alloc_pgtable()
833 cfg->arm_v7s_cfg.ttbr[1] = 0; in arm_v7s_alloc_pgtable()
Dmtk_iommu.c395 writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
800 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, in mtk_iommu_resume()
Darm-smmu.c506 cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr; in arm_smmu_init_context_bank()
521 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; in arm_smmu_init_context_bank()
522 cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; in arm_smmu_init_context_bank()
536 cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr; in arm_smmu_init_context_bank()
537 cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr; in arm_smmu_init_context_bank()
/Linux-v5.4/include/linux/
Dio-pgtable.h118 } arm_v7s_cfg; member