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Searched refs:anatop_base (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/arch/arm/mach-imx/
Danatop.c112 void __iomem *anatop_base; in imx_init_revision_from_anatop() local
119 anatop_base = of_iomap(np, 0); in imx_init_revision_from_anatop()
120 WARN_ON(!anatop_base); in imx_init_revision_from_anatop()
125 digprog = readl_relaxed(anatop_base + offset); in imx_init_revision_from_anatop()
126 iounmap(anatop_base); in imx_init_revision_from_anatop()
/Linux-v5.4/drivers/soc/imx/
Dsoc-imx8.c92 void __iomem *anatop_base; in imx8mm_soc_revision() local
99 anatop_base = of_iomap(np, 0); in imx8mm_soc_revision()
100 WARN_ON(!anatop_base); in imx8mm_soc_revision()
102 rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM); in imx8mm_soc_revision()
104 iounmap(anatop_base); in imx8mm_soc_revision()
/Linux-v5.4/drivers/clk/imx/
Dclk-vf610.c55 #define PFD_PLL1_BASE (anatop_base + 0x2b0)
56 #define PFD_PLL2_BASE (anatop_base + 0x100)
57 #define PFD_PLL3_BASE (anatop_base + 0xf0)
58 #define PLL1_CTRL (anatop_base + 0x270)
59 #define PLL2_CTRL (anatop_base + 0x30)
60 #define PLL3_CTRL (anatop_base + 0x10)
61 #define PLL4_CTRL (anatop_base + 0x70)
62 #define PLL5_CTRL (anatop_base + 0xe0)
63 #define PLL6_CTRL (anatop_base + 0xa0)
64 #define PLL7_CTRL (anatop_base + 0x20)
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Dclk-imx6sl.c101 static void __iomem *anatop_base; variable
130 if ((readl_relaxed(anatop_base + PLL_ARM) & in imx6sl_get_arm_divider_for_wait()
144 saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
147 writel_relaxed(val, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
148 while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) in imx6sl_enable_pll_arm()
151 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
211 anatop_base = base; in imx6sl_clocks_init()
Dclk-imx6q.c397 static void disable_anatop_clocks(void __iomem *anatop_base) in disable_anatop_clocks() argument
402 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); in disable_anatop_clocks()
409 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); in disable_anatop_clocks()
412 reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); in disable_anatop_clocks()
414 writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); in disable_anatop_clocks()
417 reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); in disable_anatop_clocks()
419 writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); in disable_anatop_clocks()
440 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
463 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
643 disable_anatop_clocks(anatop_base); in imx6q_clocks_init()