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Searched refs:amdgpu_ring_write (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1495 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1497 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1511 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1512 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1531 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1549 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1550 amdgpu_ring_write(ring, seq); in vcn_v2_0_dec_ring_emit_fence()
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Dvcn_v1_0.c1445 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1447 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1448 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1450 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1464 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1466 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1484 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1486 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1487 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1489 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
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Duvd_v6_0.c183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v6_0_enc_ring_test_ring()
488 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
489 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
492 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
493 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
496 amdgpu_ring_write(ring, tmp); in uvd_v6_0_hw_init()
497 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v6_0_hw_init()
500 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
501 amdgpu_ring_write(ring, 0x8); in uvd_v6_0_hw_init()
503 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
[all …]
Duvd_v4_2.c176 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
177 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
180 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
181 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
184 amdgpu_ring_write(ring, tmp); in uvd_v4_2_hw_init()
185 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v4_2_hw_init()
188 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
189 amdgpu_ring_write(ring, 0x8); in uvd_v4_2_hw_init()
191 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
192 amdgpu_ring_write(ring, 3); in uvd_v4_2_hw_init()
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Duvd_v5_0.c173 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
174 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
177 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
178 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
181 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
182 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
185 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
186 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
188 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
189 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
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Dsdma_v2_4.c236 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v2_4_ring_insert_nop()
239 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v2_4_ring_insert_nop()
260 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v2_4_ring_emit_ib()
263 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
264 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
265 amdgpu_ring_write(ring, ib->length_dw); in sdma_v2_4_ring_emit_ib()
266 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
267 amdgpu_ring_write(ring, 0); in sdma_v2_4_ring_emit_ib()
287 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v2_4_ring_emit_hdp_flush()
290 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v2_4_ring_emit_hdp_flush()
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Dsi_dma.c73 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_dma_ring_emit_ib()
74 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); in si_dma_ring_emit_ib()
75 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
76 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
96 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
97 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
98 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
99 amdgpu_ring_write(ring, seq); in si_dma_ring_emit_fence()
103 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); in si_dma_ring_emit_fence()
104 amdgpu_ring_write(ring, addr & 0xfffffffc); in si_dma_ring_emit_fence()
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Duvd_v7_0.c191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); in uvd_v7_0_enc_ring_test_ring()
552 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
553 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
557 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
558 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
562 amdgpu_ring_write(ring, tmp); in uvd_v7_0_hw_init()
563 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v7_0_hw_init()
566 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
568 amdgpu_ring_write(ring, 0x8); in uvd_v7_0_hw_init()
570 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
[all …]
Dcik_sdma.c208 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
211 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
233 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
236 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
258 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
261 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
[all …]
Dsdma_v3_0.c410 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v3_0_ring_insert_nop()
413 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v3_0_ring_insert_nop()
434 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v3_0_ring_emit_ib()
437 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
439 amdgpu_ring_write(ring, ib->length_dw); in sdma_v3_0_ring_emit_ib()
440 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
441 amdgpu_ring_write(ring, 0); in sdma_v3_0_ring_emit_ib()
461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v3_0_ring_emit_hdp_flush()
464 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in sdma_v3_0_ring_emit_hdp_flush()
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Dsdma_v5_0.c236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); in sdma_v5_0_ring_init_cond_exec()
237 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
238 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
239 amdgpu_ring_write(ring, 1); in sdma_v5_0_ring_init_cond_exec()
241 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_0_ring_init_cond_exec()
363 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v5_0_ring_insert_nop()
366 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v5_0_ring_insert_nop()
388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v5_0_ring_emit_ib()
391 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
392 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
[all …]
Dgfx_v7_0.c2104 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2105 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v7_0_ring_test_ring()
2106 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2151 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2152 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2155 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2156 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2157 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2158 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2159 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
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Dgfx_v6_0.c1808 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1809 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_test_ring()
1810 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v6_0_ring_test_ring()
1830 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1831 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | in gfx_v6_0_ring_emit_vgt_flush()
1841 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1842 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); in gfx_v6_0_ring_emit_fence()
1843 amdgpu_ring_write(ring, 0); in gfx_v6_0_ring_emit_fence()
1844 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1845 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in gfx_v6_0_ring_emit_fence()
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Dgfx_v10_0.c259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
260 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx10_kiq_set_resources()
262 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
263 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
264 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx10_kiq_set_resources()
265 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx10_kiq_set_resources()
266 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx10_kiq_set_resources()
267 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx10_kiq_set_resources()
278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx10_kiq_map_queues()
280 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx10_kiq_map_queues()
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Dgfx_v8_0.c853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
854 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v8_0_ring_test_ring()
855 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v8_0_ring_test_ring()
4215 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_cp_gfx_start()
4216 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
4218 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_cp_gfx_start()
4219 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4220 amdgpu_ring_write(ring, 0x80000000); in gfx_v8_0_cp_gfx_start()
4225 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
4228 amdgpu_ring_write(ring, in gfx_v8_0_cp_gfx_start()
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Dgfx_v9_0.c808 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
809 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | in gfx_v9_0_write_data_to_reg()
812 amdgpu_ring_write(ring, reg); in gfx_v9_0_write_data_to_reg()
813 amdgpu_ring_write(ring, 0); in gfx_v9_0_write_data_to_reg()
814 amdgpu_ring_write(ring, val); in gfx_v9_0_write_data_to_reg()
822 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
823 amdgpu_ring_write(ring, in gfx_v9_0_wait_reg_mem()
832 amdgpu_ring_write(ring, addr0); in gfx_v9_0_wait_reg_mem()
833 amdgpu_ring_write(ring, addr1); in gfx_v9_0_wait_reg_mem()
834 amdgpu_ring_write(ring, ref); in gfx_v9_0_wait_reg_mem()
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Dvce_v3_0.c841 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v3_0_ring_emit_ib()
842 amdgpu_ring_write(ring, vmid); in vce_v3_0_ring_emit_ib()
843 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
844 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
845 amdgpu_ring_write(ring, ib->length_dw); in vce_v3_0_ring_emit_ib()
851 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); in vce_v3_0_emit_vm_flush()
852 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
853 amdgpu_ring_write(ring, pd_addr >> 12); in vce_v3_0_emit_vm_flush()
855 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); in vce_v3_0_emit_vm_flush()
856 amdgpu_ring_write(ring, vmid); in vce_v3_0_emit_vm_flush()
[all …]
Dvce_v4_0.c956 amdgpu_ring_write(ring, VCE_CMD_IB_VM); in vce_v4_0_ring_emit_ib()
957 amdgpu_ring_write(ring, vmid); in vce_v4_0_ring_emit_ib()
958 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
959 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
960 amdgpu_ring_write(ring, ib->length_dw); in vce_v4_0_ring_emit_ib()
968 amdgpu_ring_write(ring, VCE_CMD_FENCE); in vce_v4_0_ring_emit_fence()
969 amdgpu_ring_write(ring, addr); in vce_v4_0_ring_emit_fence()
970 amdgpu_ring_write(ring, upper_32_bits(addr)); in vce_v4_0_ring_emit_fence()
971 amdgpu_ring_write(ring, seq); in vce_v4_0_ring_emit_fence()
972 amdgpu_ring_write(ring, VCE_CMD_TRAP); in vce_v4_0_ring_emit_fence()
[all …]
Dsdma_v4_0.c679 amdgpu_ring_write(ring, ring->funcs->nop | in sdma_v4_0_ring_insert_nop()
682 amdgpu_ring_write(ring, ring->funcs->nop); in sdma_v4_0_ring_insert_nop()
703 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | in sdma_v4_0_ring_emit_ib()
706 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
707 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
708 amdgpu_ring_write(ring, ib->length_dw); in sdma_v4_0_ring_emit_ib()
709 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
710 amdgpu_ring_write(ring, 0); in sdma_v4_0_ring_emit_ib()
720 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | in sdma_v4_0_wait_reg_mem()
726 amdgpu_ring_write(ring, addr0); in sdma_v4_0_wait_reg_mem()
[all …]
Damdgpu_vce.c1041 amdgpu_ring_write(ring, VCE_CMD_IB); in amdgpu_vce_ring_emit_ib()
1042 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1043 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in amdgpu_vce_ring_emit_ib()
1044 amdgpu_ring_write(ring, ib->length_dw); in amdgpu_vce_ring_emit_ib()
1059 amdgpu_ring_write(ring, VCE_CMD_FENCE); in amdgpu_vce_ring_emit_fence()
1060 amdgpu_ring_write(ring, addr); in amdgpu_vce_ring_emit_fence()
1061 amdgpu_ring_write(ring, upper_32_bits(addr)); in amdgpu_vce_ring_emit_fence()
1062 amdgpu_ring_write(ring, seq); in amdgpu_vce_ring_emit_fence()
1063 amdgpu_ring_write(ring, VCE_CMD_TRAP); in amdgpu_vce_ring_emit_fence()
1064 amdgpu_ring_write(ring, VCE_CMD_END); in amdgpu_vce_ring_emit_fence()
[all …]
Damdgpu_vcn.c391 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in amdgpu_vcn_dec_ring_test_ring()
392 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_dec_ring_test_ring()
556 amdgpu_ring_write(ring, VCN_ENC_CMD_END); in amdgpu_vcn_enc_ring_test_ring()
722 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.jpeg_pitch, 0)); in amdgpu_vcn_jpeg_ring_test_ring()
723 amdgpu_ring_write(ring, 0xDEADBEEF); in amdgpu_vcn_jpeg_ring_test_ring()
Damdgpu_amdkfd_gfx_v9.c651 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in invalidate_tlbs_with_kiq()
652 amdgpu_ring_write(ring, in invalidate_tlbs_with_kiq()
Damdgpu_ring.c98 amdgpu_ring_write(ring, ring->funcs->nop); in amdgpu_ring_insert_nop()
Damdgpu_amdkfd_gfx_v10.c812 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in invalidate_tlbs_with_kiq()
813 amdgpu_ring_write(ring, in invalidate_tlbs_with_kiq()
Damdgpu_ring.h289 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() function