Searched refs:allowed_sclk_vddc_table (Results 1 – 2 of 2) sorted by relevance
3444 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_setup_default_dpm_tables() local3452 if (allowed_sclk_vddc_table == NULL) in ci_setup_default_dpm_tables()3454 if (allowed_sclk_vddc_table->count < 1) in ci_setup_default_dpm_tables()3480 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3483 allowed_sclk_vddc_table->entries[i].clk)) { in ci_setup_default_dpm_tables()3485 allowed_sclk_vddc_table->entries[i].clk; in ci_setup_default_dpm_tables()3505 for (i = 0; i < allowed_sclk_vddc_table->count; i++) { in ci_setup_default_dpm_tables()3507 allowed_sclk_vddc_table->entries[i].v; in ci_setup_default_dpm_tables()3512 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()4920 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table = in ci_set_private_data_variables_based_on_pptable() local[all …]
2458 …struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_depende… in smu7_set_private_data_based_on_pptable_v0() local2462 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, in smu7_set_private_data_based_on_pptable_v0()2465 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, in smu7_set_private_data_based_on_pptable_v0()2476 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; in smu7_set_private_data_based_on_pptable_v0()2477 …data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->co… in smu7_set_private_data_based_on_pptable_v0()2480 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; in smu7_set_private_data_based_on_pptable_v0()2484 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; in smu7_set_private_data_based_on_pptable_v0()
