| /Linux-v5.4/tools/perf/Documentation/ |
| D | perf-c2c.txt | 32 for cachelines with highest contention - highest number of HITM accesses.
167 - sum of all cachelines accesses
170 - cacheline percentage of all Remote/Local HITM accesses
176 Total - all store accesses
177 L1Hit - store accesses that hit L1
178 L1Hit - store accesses that missed L1
181 - count of local and remote DRAM accesses
184 - count of all accesses that missed LLC
187 - sum of all load accesses
198 - % of Remote/Local HITM accesses for given offset within cacheline
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| /Linux-v5.4/Documentation/i2c/ |
| D | i2c-topology.rst | 152 This means that accesses to D2 are lockout out for the full duration
153 of the entire operation. But accesses to D3 are possibly interleaved
216 This means that accesses to both D2 and D3 are locked out for the full
261 When device D1 is accessed, accesses to D2 are locked out for the
263 are locked). But accesses to D3 and D4 are possibly interleaved at
264 any point. Accesses to D3 locks out D1 and D2, but accesses to D4
282 When device D1 is accessed, accesses to D2 and D3 are locked out
284 root adapter). But accesses to D4 are possibly interleaved at any
295 mux. In that case, any interleaved accesses to D4 might close M2
316 When D1 is accessed, accesses to D2 are locked out for the full
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| /Linux-v5.4/drivers/acpi/acpica/ |
| D | exprep.c | 65 u32 accesses; in acpi_ex_generate_access() local
115 accesses = field_end_offset - field_start_offset; in acpi_ex_generate_access()
124 accesses)); in acpi_ex_generate_access()
128 if (accesses <= 1) { in acpi_ex_generate_access()
140 if (accesses < minimum_accesses) { in acpi_ex_generate_access()
141 minimum_accesses = accesses; in acpi_ex_generate_access()
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| /Linux-v5.4/Documentation/ |
| D | unaligned-memory-access.txt | 15 unaligned accesses, why you need to write code that doesn't cause them,
22 Unaligned memory accesses occur when you try to read N bytes of data starting
59 - Some architectures are able to perform unaligned memory accesses
61 - Some architectures raise processor exceptions when unaligned accesses
64 - Some architectures raise processor exceptions when unaligned accesses
72 memory accesses to happen, your code will not work correctly on certain
103 to pad structures so that accesses to fields are suitably aligned (assuming
136 lead to unaligned accesses when accessing fields that do not satisfy
183 Here is another example of some code that could cause unaligned accesses::
192 This code will cause unaligned accesses every time the data parameter points
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| D | atomic_t.txt | 194 smp_mb__before_atomic() orders all earlier accesses against the RMW op
195 itself and all accesses following it, and smp_mb__after_atomic() orders all
196 later accesses against the RMW op and all accesses preceding it. However,
197 accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
|
| D | memory-barriers.txt | 77 - Acquires vs memory accesses.
78 - Acquires vs I/O accesses.
158 The set of accesses as seen by the memory system in the middle can be arranged
231 (*) On any given CPU, dependent memory accesses will be issued in order, with
291 (*) It _must_ be assumed that overlapping memory accesses may be merged or
498 an ACQUIRE on a given variable, all memory accesses preceding any prior
500 words, within a given variable's critical section, all accesses of all
529 (*) There is no guarantee that any of the memory accesses specified before a
532 access queue that accesses of the appropriate type may not cross.
537 of the first CPU's accesses occur, but see the next point:
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| /Linux-v5.4/Documentation/devicetree/bindings/ |
| D | common-properties.txt | 13 - big-endian: Boolean; force big endian register accesses
16 - little-endian: Boolean; force little endian register accesses
19 - native-endian: Boolean; always use register accesses matched to the
30 default to LE for their MMIO accesses.
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| /Linux-v5.4/tools/memory-model/ |
| D | linux-kernel.cat | 160 (* Plain accesses and data races *)
163 (* Warn about plain writes and marked accesses in the same region *)
164 let mixed-accesses = ([Plain & W] ; (po-loc \ barrier) ; [Marked]) |
166 flag ~empty mixed-accesses as mixed-accesses
173 (* Boundaries for lifetimes of plain accesses *)
181 (* Visibility and executes-before for plain accesses *)
191 (* Coherence requirements for plain accesses *)
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| /Linux-v5.4/Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 10 resource describes the data bus connected to the NAND flash and all accesses
23 location used to guard against bus reordering with regards to accesses to
26 read to ensure that the GPIO accesses have completed.
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| /Linux-v5.4/tools/memory-model/litmus-tests/ |
| D | MP+polocks.litmus | 9 * given lock), a CPU is not only guaranteed to see the accesses that other
11 * to see all prior accesses by those other CPUs.
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| D | MP+porevlocks.litmus | 9 * given lock), a CPU is not only guaranteed to see the accesses that other
11 * see all prior accesses by those other CPUs.
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| D | README | 40 litmus test is visible to an external process whose accesses are
141 spin_lock() sufficient to make ordering apparent to accesses
150 to make ordering apparent to accesses by a process that does
173 Each class defines the pattern of accesses and of the variables accessed.
206 accesses with descriptions of the second access in the pair.
220 to a different variable ("d"), and both accesses are reads ("RR").
246 The descriptors that describe connections between consecutive accesses
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| /Linux-v5.4/arch/mips/kvm/ |
| D | Kconfig | 66 bool "Maintain counters for COP0 accesses"
69 Maintain statistics for Guest COP0 accesses.
70 A histogram of COP0 accesses is printed when the VM is
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| /Linux-v5.4/Documentation/driver-api/ |
| D | device-io.rst | 30 part of the CPU's address space is interpreted not as accesses to
31 memory, but as accesses to a device. Some architectures define devices
54 historical accident, these are named byte, word, long and quad accesses.
55 Both read and write accesses are supported; there is no prefetch support
127 addresses is generally not as fast as accesses to the memory mapped
137 allow 8-bit, 16-bit and 32-bit accesses; also known as byte, word and
143 that accesses to their ports are slowed down. This functionality is
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| /Linux-v5.4/Documentation/hwmon/ |
| D | w83627hf.rst | 5 * Winbond W83627HF (ISA accesses ONLY)
41 This driver implements support for ISA accesses *only* for
45 This driver supports ISA accesses, which should be more reliable
46 than i2c accesses. Also, for Tyan boards which contain both a
51 If you really want i2c accesses for these Super I/O chips,
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| /Linux-v5.4/lib/ |
| D | Kconfig.kasan | 22 designed to find out-of-bounds accesses and use-after-free bugs.
48 out-of-bounds accesses for stack and global variables and for inline
51 out-of-bounds accesses for global variables yet.
100 memory accesses. This is faster than outline (in some workloads
150 out of bounds accesses, use after free. It is useful for testing
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| D | Kconfig.ubsan | 36 This option disables the check of unaligned memory accesses.
39 accesses may produce a lot of false positives.
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| /Linux-v5.4/tools/memory-model/Documentation/ |
| D | cheatsheet.txt | 29 SELF: Orders self, as opposed to accesses before and/or after
30 SV: Orders later accesses to the same variable
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| D | recipes.txt | 32 compiler can emit whatever code it likes for normal accesses,
39 must be properly aligned and all accesses to that variable must
41 your full-ordering warranty, as do undersized accesses that load
44 4. If there are multiple CPUs, accesses to shared variables should
125 However, it is not necessarily the case that accesses ordered by
232 The smp_store_release() macro orders any prior accesses against the
234 subsequent accesses. Therefore, if the final value of r0 is the value 1,
274 against later accesses that depend on the value loaded. A dependency
528 based on the relation between the accesses linking successive CPUs in a
551 linking the memory accesses for the outcome in question:
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| /Linux-v5.4/Documentation/process/ |
| D | volatile-considered-harmful.rst | 39 meaning that data accesses will not be optimized across them. So the
43 accesses to that data.
53 registers. Within the kernel, register accesses, too, should be protected
55 accesses within a critical section. But, within the kernel, I/O memory
56 accesses are always done through accessor functions; accessing I/O memory
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| /Linux-v5.4/Documentation/devicetree/bindings/thermal/ |
| D | mediatek-thermal.txt | 5 instead it directly controls the AUXADC via AHB bus accesses. For this reason
7 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
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| /Linux-v5.4/Documentation/devicetree/bindings/pci/ |
| D | designware-pcie-ecam.txt | 8 to reconfigure ATU windows for config and/or IO space accesses at runtime.
12 requires special config space accessors that filter accesses to device #1
|
| /Linux-v5.4/Documentation/devicetree/bindings/iommu/ |
| D | msm,iommu-v0.txt | 27 required for iommu's register accesses.
29 required by iommu for bus accesses.
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| /Linux-v5.4/Documentation/dev-tools/ |
| D | ubsan.rst | 78 Detection of unaligned accesses controlled through the separate option -
80 unaligned accesses (CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y). One could
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| /Linux-v5.4/Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-sdram-edac.txt | 2 The EDAC accesses a range of registers in the SDRAM controller.
|
