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/Linux-v5.4/drivers/clk/sunxi-ng/
Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
46 .width = _width, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
57 .width = _width, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
[all …]
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
23 .width = _width, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
35 .width = _width, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
51 _reg, _shift, _width, _gate, \ argument
55 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
66 _shift, _width, _gate, _flags) \ argument
68 _reg, _shift, _width, _gate, \
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
74 _reg, _shift, _width, 0, _flags)
Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
23 .width = _width, \
/Linux-v5.4/drivers/clk/actions/
Dowl-pll.h42 _width, _min_mul, _max_mul, _delay, _table) \ argument
48 .width = _width, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
59 _width, _min_mul, _max_mul, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
74 _width, _min_mul, _max_mul, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
89 _width, _min_mul, _max_mul, \
Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
31 .width = _width, \
35 _shift, _width, _flags) \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
33 .width = _width, \
39 _shift, _width, _table, _div_flags, _flags) \ argument
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument
39 .width = _width, \
45 _shift, _width, _table, _fct_flags, _flags) \ argument
48 _width, _fct_flags, _table), \
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mtk.h82 _width, _gate, _flags, _muxflags) { \ argument
87 .mux_width = _width, \
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
104 _shift, _width, _gate, _flags, 0)
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
116 _shift, _width, CLK_SET_RATE_PARENT)
118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
123 .mux_width = _width, \
[all …]
Dclk-mux.h46 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
55 .mux_width = _width, \
65 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
68 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
73 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
77 _width, _gate, _upd_ofs, _upd, \
Dclk-mt8516.c467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
473 .div_width = _width, \
/Linux-v5.4/drivers/clk/sprd/
Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
35 .width = _width, \
40 _reg, _shift, _width, \ argument
43 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
55 _shift, _width, _flags) \ argument
57 _reg, _shift, _width, _flags)
Ddiv.h27 #define _SPRD_DIV_CLK(_shift, _width) \ argument
30 .width = _width, \
39 _shift, _width, _flags) \ argument
41 .div = _SPRD_DIV_CLK(_shift, _width), \
/Linux-v5.4/drivers/clk/zte/
Dclk.h98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
102 .mask = BIT(_width) - 1, \
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
115 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
122 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
127 .width = _width, \
/Linux-v5.4/drivers/clk/pistachio/
Dclk.h59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
63 .width = _width, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
73 .width = _width, \
/Linux-v5.4/drivers/clk/bcm/
Dclk-kona.h299 #define DIVIDER(_offset, _shift, _width) \ argument
303 .u.s.width = (_width), \
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
313 .u.s.width = (_width), \
350 #define SELECTOR(_offset, _shift, _width) \ argument
354 .width = (_width), \
/Linux-v5.4/drivers/pinctrl/berlin/
Dberlin.h37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
41 .bit_width = _width, \
/Linux-v5.4/drivers/clk/meson/
Dclk-phase.c13 #define phase_step(_width) (360 / (1 << (_width))) argument
Daxg-audio.c59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \ argument
64 .width = (_width), \
245 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ argument
252 .width = (_width), \
257 .width = (_width), \
262 .width = (_width), \
/Linux-v5.4/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1386 #define GET_BITS(_var, _index, _width) \ argument
1387 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1389 #define SET_BITS(_var, _index, _width, _val) \ argument
1391 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1392 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1395 #define GET_BITS_LE(_var, _index, _width) \ argument
1396 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1398 #define SET_BITS_LE(_var, _index, _width, _val) \ argument
1400 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1402 ((0x1 << (_width)) - 1)) << (_index))); \
/Linux-v5.4/drivers/clk/
Dclk-stm32mp1.c1119 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1129 .width = _width,\
1136 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1137 DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1140 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1150 .width = _width,\
1246 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1251 .width = _width,\
1259 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument
1260 _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
[all …]
/Linux-v5.4/include/uapi/linux/
Dv4l2-dv-timings.h25 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
26 { .bt = { _width , ## args } }
28 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
29 .bt = { _width , ## args }
/Linux-v5.4/drivers/soc/sunxi/
Dsunxi_sram.c51 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ argument
56 .width = _width, \
/Linux-v5.4/drivers/net/ethernet/intel/ice/
Dice_lan_tx_rx.h303 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ argument
306 .width = _width, \
/Linux-v5.4/drivers/gpu/drm/gma500/
Dframebuffer.c37 #define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16) argument

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