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Searched refs:_reg (Results 1 – 25 of 116) sorted by relevance

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/Linux-v5.4/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1440 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1441 ioread32((_pdata)->xgmac_regs + _reg)
1443 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1444 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1445 _reg##_##_field##_INDEX, \
1446 _reg##_##_field##_WIDTH)
1448 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1449 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1451 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1453 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
[all …]
/Linux-v5.4/drivers/regulator/
Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
66 .reg = prefix ## _reg, \
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
84 .reg = prefix ## _reg, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
99 .reg = prefix ## _reg, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
[all …]
/Linux-v5.4/drivers/clk/zte/
Dclk.h37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
39 .reg_base = (void __iomem *) _reg, \
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
53 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
63 .reg = (void __iomem *) _reg, \
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
101 .reg = (void __iomem *) _reg, \
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
115 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
[all …]
/Linux-v5.4/drivers/clk/sunxi-ng/
Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
23 .reg = _reg, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
35 .reg = _reg, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
47 .reg = _reg, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
63 .reg = _reg, \
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
75 .reg = _reg, \
Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
95 .reg = _reg, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
113 _reg, \ argument
122 .reg = _reg, \
130 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
135 _reg, _mshift, _mwidth, \
139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
144 _reg, _mshift, _mwidth, \
[all …]
Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
46 .reg = _reg, \
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
66 .reg = _reg, \
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
79 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
103 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
111 .reg = _reg, \
Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
52 .reg = _reg, \
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
76 .reg = _reg, \
86 _reg, _min_rate, \ argument
102 .reg = _reg, \
112 _parent, _reg, \ argument
131 .reg = _reg, \
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
150 .reg = _reg, \
Dccu_mux.h51 _reg, _shift, _width, _gate, \ argument
57 .reg = _reg, \
65 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
68 _reg, _shift, _width, _gate, \
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
74 _reg, _shift, _width, 0, _flags)
/Linux-v5.4/drivers/clk/pistachio/
Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
22 .reg = _reg, \
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
42 .reg = _reg, \
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
62 .reg = _reg, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
72 .reg = _reg, \
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
122 .reg_base = _reg, \
[all …]
/Linux-v5.4/arch/arm/mach-mmp/
Dclock.h25 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ argument
27 .clk_rst = APBC_##_reg, \
33 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ argument
35 .clk_rst = APBC_##_reg, \
41 #define APMU_CLK(_name, _reg, _eval, _rate) \ argument
43 .clk_rst = APMU_##_reg, \
49 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ argument
51 .clk_rst = APMU_##_reg, \
/Linux-v5.4/arch/mips/include/asm/mach-pic32/
Dpic32.h14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument
15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument
16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
/Linux-v5.4/drivers/clk/meson/
Daxg-audio.c27 #define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \ argument
30 .offset = (_reg), \
42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \ argument
45 .offset = (_reg), \
59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \ argument
62 .offset = (_reg), \
126 #define AUD_MST_MUX(_name, _reg, _flag) \ argument
127 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
130 #define AUD_MST_MCLK_MUX(_name, _reg) \ argument
131 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
[all …]
Dclk-regmap.h114 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
117 .offset = (_reg), \
129 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
130 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
132 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
/Linux-v5.4/drivers/clk/mediatek/
Dclk-mtk.h81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
85 .mux_reg = _reg, \
88 .gate_reg = _reg, \
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
103 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
115 MUX_FLAGS(_id, _name, _parents, _reg, \
118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
[all …]
/Linux-v5.4/drivers/clk/actions/
Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
44 .reg = _reg, \
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
29 .reg = _reg, \
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
29 .reg = _reg, \
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
/Linux-v5.4/drivers/clk/sprd/
Dgate.h21 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
29 .reg = _reg, \
37 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
39 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
43 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
45 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
Dpll.h64 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
78 .reg = _reg, \
86 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
89 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
93 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
Dcomposite.h21 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
28 .reg = _reg, \
36 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
38 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
/Linux-v5.4/drivers/media/tuners/
Dmc44s803_priv.h179 #define MC44S803_REG_SM(_val, _reg) \ argument
180 (((_val) << _reg##_S) & (_reg))
183 #define MC44S803_REG_MS(_val, _reg) \ argument
184 (((_val) & (_reg)) >> _reg##_S)
/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dreg.h80 #define REG_50080_TO_PIPE(_reg) ({ \ argument
81 typeof(_reg) (reg) = (_reg); \
87 #define REG_50080_TO_PLANE(_reg) ({ \ argument
88 typeof(_reg) (reg) = (_reg); \
/Linux-v5.4/arch/mips/include/asm/
Dkvm_host.h471 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ argument
474 return cop0->reg[(_reg)][(sel)]; \
479 cop0->reg[(_reg)][(sel)] = val; \
483 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ argument
487 cop0->reg[(_reg)][(sel)] |= val; \
492 cop0->reg[(_reg)][(sel)] &= ~val; \
499 cop0->reg[(_reg)][(sel)] &= ~_mask; \
500 cop0->reg[(_reg)][(sel)] |= val & _mask; \
504 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ argument
508 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
[all …]
/Linux-v5.4/include/linux/
Dsh_clk.h151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
154 .enable_reg = (void __iomem *)_reg, \
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
178 .enable_reg = (void __iomem *)_reg, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
191 .enable_reg = (void __iomem *)_reg, \
205 #define SH_CLK_FSIDIV(_reg, _parent) \ argument
207 .enable_reg = (void __iomem *)_reg, \
/Linux-v5.4/drivers/gpu/drm/msm/adreno/
Da6xx_gpu.h33 #define A6XX_PROTECT_RW(_reg, _len) \ argument
35 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
42 #define A6XX_PROTECT_RDONLY(_reg, _len) \ argument
43 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))

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