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Searched refs:_REG (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/meson/
Dmeson_viu.c83 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
85 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
87 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
89 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
91 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
93 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
95 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
100 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
Dmeson_venc.c1042 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
1044 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1045 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1053 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
1056 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
1059 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1062 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1067 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
1069 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
Dmeson_crtc.c90 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
95 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
99 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
102 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
126 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
130 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
133 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
182 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
236 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
[all …]
Dmeson_dw_hdmi.c415 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
489 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
491 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
495 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
497 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
501 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
503 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
507 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
512 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
515 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
[all …]
Dmeson_plane.c148 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
155 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
162 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
169 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_plane_atomic_update()
332 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_plane_atomic_disable()
335 priv->io_base + _REG(VPP_MISC)); in meson_plane_atomic_disable()
Dmeson_drv.c69 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); in meson_irq()
151 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
155 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
160 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
164 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
Dmeson_overlay.c517 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_overlay_atomic_disable()
518 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); in meson_overlay_atomic_disable()
519 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); in meson_overlay_atomic_disable()
520 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); in meson_overlay_atomic_disable()
523 priv->io_base + _REG(VPP_MISC)); in meson_overlay_atomic_disable()
Dmeson_venc_cvbs.c175 priv->io_base + _REG(VENC_VDAC_DACSEL0)); in meson_venc_cvbs_encoder_enable()
Dmeson_registers.h12 #define _REG(reg) ((reg) << 2) macro
/Linux-v5.4/sound/soc/qcom/
Dlpass-lpaif-reg.h120 LPAIF_RDMA##reg##_REG(v, chan) : \
121 LPAIF_WRDMA##reg##_REG(v, chan)
/Linux-v5.4/drivers/iommu/
Dintel-iommu-debugfs.c34 { DMAR_##_reg_##_REG, __stringify(_reg_) }