Home
last modified time | relevance | path

Searched refs:_MASKED_BIT_ENABLE (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dmmio_context.h57 (_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
58 ((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
Dhandlers.c1698 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); in ring_mode_mmio_write()
1700 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); in ring_mode_mmio_write()
1703 if (data & _MASKED_BIT_ENABLE(1)) { in ring_mode_mmio_write()
1709 data & _MASKED_BIT_ENABLE(2)) { in ring_mode_mmio_write()
1718 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || in ring_mode_mmio_write()
1719 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) in ring_mode_mmio_write()
1724 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) in ring_mode_mmio_write()
1786 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) in ring_reset_ctl_write()
1801 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
1804 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8)) in csfe_chicken1_mmio_write()
[all …]
Dmmio_context.c460 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in is_inhibit_context()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_ringbuffer.c583 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in flush_cs_tlb()
607 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
867 _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); in rcs_resume()
871 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in rcs_resume()
880 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in rcs_resume()
886 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); in rcs_resume()
891 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | in rcs_resume()
892 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); in rcs_resume()
905 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in rcs_resume()
1618 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
[all …]
Dintel_workarounds.c165 wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val)); in wa_masked_en()
181 wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
555 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); in icl_ctx_workarounds_init()
Dintel_lrc.c2318 mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE); in enable_execlists()
2320 mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE); in enable_execlists()
3202 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); in execlists_init_reg_state()
3326 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in populate_lr_context()
Dintel_reset.c470 intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); in gen8_engine_reset_prepare()
Dintel_engine_cs.c866 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); in intel_engine_stop_cs()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_gem_fence_reg.c877 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in intel_gt_init_swizzling()
881 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in intel_gt_init_swizzling()
885 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in intel_gt_init_swizzling()
Dintel_pm.c394 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in _intel_set_memory_cxsr()
405 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in _intel_set_memory_cxsr()
7930 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in cherryview_enable_rc6()
8021 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in valleyview_enable_rc6()
8967 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); in ilk_init_clock_gating()
9035 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); in gen6_init_clock_gating()
9078 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); in gen6_init_clock_gating()
9086 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); in gen6_init_clock_gating()
9196 _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE)); in icl_init_clock_gating()
9216 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); in cnl_init_clock_gating()
[all …]
Di915_perf.c1976 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | in gen8_enable_metric_set()
3205 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); in mask_reg_value()
3212 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); in mask_reg_value()
Dintel_uncore.c89 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
Di915_gem_gtt.c1573 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen7_ppgtt_enable()
1599 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
Di915_reg.h272 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro
/Linux-v5.4/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c885 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \ in ctx_save_restore_disabled()
1016 irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); in guc_interrupts_capture()
Dintel_uc_fw.c473 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); in uc_fw_xfer()