Searched refs:XGMAC_DMA_CH_TX_CONTROL (Results 1 – 2 of 2) sorted by relevance
68 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()72 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()272 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()274 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()285 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()287 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()460 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()467 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
337 #define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x))) macro