Searched refs:WRITE_DATA_DST_SEL (Results 1 – 15 of 15) sorted by relevance
153 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
144 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
262 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
896 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5211 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5219 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5227 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5235 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6387 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6396 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7207 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7240 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3289 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4099 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4107 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4115 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4123 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
810 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()899 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5282 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5291 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5315 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5337 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
405 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()4556 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()4565 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()4692 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()4726 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
2369 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3756 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5699 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5713 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5720 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5731 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5742 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5082 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5097 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5105 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
