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Searched refs:WREG8 (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/mgag200/
Dmgag200_mode.c42 WREG8(DAC_INDEX + MGA1064_INDEX, 0); in mga_crtc_load_lut()
62 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); in mga_crtc_load_lut()
63 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); in mga_crtc_load_lut()
64 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); in mga_crtc_load_lut()
70 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8); in mga_crtc_load_lut()
71 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); in mga_crtc_load_lut()
72 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8); in mga_crtc_load_lut()
305 WREG8(MGAREG_CRTC_INDEX, 0x1e); in mga_g200wb_set_plls()
308 WREG8(MGAREG_CRTC_DATA, tmp+1); in mga_g200wb_set_plls()
312 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mga_g200wb_set_plls()
[all …]
Dmgag200_drv.h39 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) macro
49 WREG8(ATTR_INDEX, reg); \
50 WREG8(ATTR_DATA, v); \
55 WREG8(MGAREG_SEQ_INDEX, reg); \
56 WREG8(MGAREG_SEQ_DATA, v); \
61 WREG8(MGAREG_CRTC_INDEX, reg); \
62 WREG8(MGAREG_CRTC_DATA, v); \
68 WREG8(MGAREG_CRTCEXT_INDEX, reg); \
69 WREG8(MGAREG_CRTCEXT_DATA, v); \
77 WREG8(GFX_INDEX, reg); \
[all …]
Dmgag200_cursor.c21 WREG8(MGA_CURPOSXL, 0); in mga_hide_cursor()
22 WREG8(MGA_CURPOSXH, 0); in mga_hide_cursor()
57 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
58 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
74 WREG8(MGA_CURPOSXL, 0); in mga_crtc_cursor_set()
75 WREG8(MGA_CURPOSXH, 0); in mga_crtc_cursor_set()
247 WREG8(MGA_CURPOSXL, x & 0xff); in mga_crtc_cursor_move()
248 WREG8(MGA_CURPOSXH, (x>>8) & 0xff); in mga_crtc_cursor_move()
250 WREG8(MGA_CURPOSYL, y & 0xff); in mga_crtc_cursor_move()
251 WREG8(MGA_CURPOSYH, (y>>8) & 0xff); in mga_crtc_cursor_move()
Dmgag200_i2c.c39 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); in mga_i2c_read_gpio()
47 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); in mga_i2c_set_gpio()
/Linux-v5.4/drivers/gpu/drm/cirrus/
Dcirrus_drv.h37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg)) macro
46 WREG8(SEQ_INDEX, reg); \
47 WREG8(SEQ_DATA, v); \
55 WREG8(CRT_INDEX, reg); \
56 WREG8(CRT_DATA, v); \
64 WREG8(GFX_INDEX, reg); \
65 WREG8(GFX_DATA, v); \
81 WREG8(VGA_DAC_MASK, v); \
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_ai.c37 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_ai_mailbox_send_ack()
42 WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_ai_mailbox_set_valid()
Damdgpu.h1061 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) macro
/Linux-v5.4/drivers/gpu/drm/radeon/
Dradeon_legacy_tv.c289 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
291 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
Dr100.c2886 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2899 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
3790 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3821 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3834 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); in r100_vga_render_disable()
Dradeon_display.c71 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); in avivo_crtc_load_lut()
206 WREG8(RADEON_PALETTE_INDEX, 0); in legacy_crtc_load_lut()
Dradeon.h2509 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) macro