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Searched refs:WREG32_SOC15 (Results 1 – 25 of 43) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v2_0.c54 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in gfxhub_v2_0_init_gart_pt_regs()
57 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in gfxhub_v2_0_init_gart_pt_regs()
65 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
67 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
70 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
72 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
81 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
82 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_0_init_system_aperture_regs()
83 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); in gfxhub_v2_0_init_system_aperture_regs()
86 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
[all …]
Dmmhub_v2_0.c38 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_v2_0_init_gart_pt_regs()
41 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_v2_0_init_gart_pt_regs()
49 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
51 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
54 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
56 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
66 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
67 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); in mmhub_v2_0_init_system_aperture_regs()
68 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); in mmhub_v2_0_init_system_aperture_regs()
71 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v2_0_init_system_aperture_regs()
[all …]
Dmmhub_v1_0.c78 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
80 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
83 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
85 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
95 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); in mmhub_v1_0_init_system_aperture_regs()
96 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
97 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
100 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v1_0_init_system_aperture_regs()
110 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v1_0_init_system_aperture_regs()
114 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v1_0_init_system_aperture_regs()
[all …]
Dvega10_ih.c59 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_enable_interrupts()
74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_enable_interrupts()
90 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_enable_interrupts()
115 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_disable_interrupts()
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in vega10_ih_disable_interrupts()
120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in vega10_ih_disable_interrupts()
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_disable_interrupts()
138 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); in vega10_ih_disable_interrupts()
139 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); in vega10_ih_disable_interrupts()
155 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_disable_interrupts()
[all …]
Dvcn_v1_0.c301 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
305 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume_spg_mode()
308 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_spg_mode()
317 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume_spg_mode()
320 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
322 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
324 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v1_0_mc_resume_spg_mode()
[all …]
Dvcn_v2_5.c387 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
389 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
391 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
394 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
396 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
399 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
402 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
405 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
407 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
409 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
[all …]
Dvcn_v2_0.c370 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
372 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
374 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
377 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
379 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
382 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
386 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_0_mc_resume()
389 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
391 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
393 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_0_mc_resume()
[all …]
Dpsp_v12_0.c116 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v12_0_bootloader_load_sysdrv()
119 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v12_0_bootloader_load_sysdrv()
157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v12_0_bootloader_load_sos()
160 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v12_0_bootloader_load_sos()
182 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); in psp_v12_0_reroute_ih()
183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v12_0_reroute_ih()
184 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v12_0_reroute_ih()
194 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); in psp_v12_0_reroute_ih()
195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v12_0_reroute_ih()
196 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v12_0_reroute_ih()
[all …]
Duvd_v7_0.c140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
660 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
664 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
668 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in uvd_v7_0_mc_resume()
671 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
673 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
676 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
680 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v7_0_mc_resume()
[all …]
Dmes_v10_1.c194 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
197 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_enable()
204 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); in mes_v10_1_enable()
208 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
216 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
241 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); in mes_v10_1_load_microcode()
248 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_load_microcode()
252 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, in mes_v10_1_load_microcode()
254 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, in mes_v10_1_load_microcode()
258 WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF); in mes_v10_1_load_microcode()
[all …]
Dpsp_v3_1.c156 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sysdrv()
159 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sysdrv()
219 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sos()
222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sos()
274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); in psp_v3_1_reroute_ih()
275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v3_1_reroute_ih()
276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v3_1_reroute_ih()
286 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); in psp_v3_1_reroute_ih()
287 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v3_1_reroute_ih()
288 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v3_1_reroute_ih()
[all …]
Dgfxhub_v1_0.c58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
99 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v1_0_init_system_aperture_regs()
101 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in gfxhub_v1_0_init_system_aperture_regs()
105 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in gfxhub_v1_0_init_system_aperture_regs()
107 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in gfxhub_v1_0_init_system_aperture_regs()
181 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_0_enable_system_domain()
186 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, in gfxhub_v1_0_disable_identity_aperture()
[all …]
Dnavi10_ih.c51 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_enable_interrupts()
68 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_disable_interrupts()
70 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in navi10_ih_disable_interrupts()
71 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in navi10_ih_disable_interrupts()
123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); in navi10_ih_irq_init()
124 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); in navi10_ih_irq_init()
136 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); in navi10_ih_irq_init()
140 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_irq_init()
143 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, in navi10_ih_irq_init()
145 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, in navi10_ih_irq_init()
[all …]
Dgfx_v10_0.c1112 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
1122 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
1519 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v10_0_select_se_sh()
1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v10_0_init_compute_vmid()
1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v10_0_init_compute_vmid()
1706 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); in gfx_v10_0_tcp_harvest()
1712 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); in gfx_v10_0_tcp_harvest()
1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v10_0_constants_init()
1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); in gfx_v10_0_constants_init()
1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v10_0_enable_gui_idle_interrupt()
[all …]
Damdgpu_vcn.h60 ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
61 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
71 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
72 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
73 WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
105 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \
115 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); \
116 WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \
Dnbio_v7_0.c38 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, in nbio_v7_0_remap_hdp_registers()
40 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, in nbio_v7_0_remap_hdp_registers()
57 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v7_0_mc_access_enable()
60 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v7_0_mc_access_enable()
137 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v7_0_ih_doorbell_range()
144 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); in nbio_7_0_read_syshub_ind_mmr()
153 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); in nbio_7_0_write_syshub_ind_mmr()
154 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); in nbio_7_0_write_syshub_ind_mmr()
237 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v7_0_ih_control()
245 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v7_0_ih_control()
Dnbio_v7_4.c55 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, in nbio_v7_4_remap_hdp_registers()
57 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, in nbio_v7_4_remap_hdp_registers()
74 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v7_4_mc_access_enable()
77 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v7_4_mc_access_enable()
167 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v7_4_enable_doorbell_selfring_aperture()
169 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v7_4_enable_doorbell_selfring_aperture()
173 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); in nbio_v7_4_enable_doorbell_selfring_aperture()
187 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v7_4_ih_doorbell_range()
238 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v7_4_ih_control()
246 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v7_4_ih_control()
Dpsp_v11_0.c237 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_kdb()
240 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_kdb()
279 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_sysdrv()
282 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_sysdrv()
320 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_sos()
323 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_sos()
345 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); in psp_v11_0_reroute_ih()
346 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v11_0_reroute_ih()
347 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v11_0_reroute_ih()
357 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); in psp_v11_0_reroute_ih()
[all …]
Dnbio_v2_3.c48 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v2_3_mc_access_enable()
52 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v2_3_mc_access_enable()
134 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v2_3_enable_doorbell_selfring_aperture()
136 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v2_3_enable_doorbell_selfring_aperture()
140 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, in nbio_v2_3_enable_doorbell_selfring_aperture()
162 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v2_3_ih_doorbell_range()
170 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v2_3_ih_control()
184 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v2_3_ih_control()
Dnbio_v6_1.c46 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v6_1_mc_access_enable()
50 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v6_1_mc_access_enable()
104 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v6_1_enable_doorbell_selfring_aperture()
106 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v6_1_enable_doorbell_selfring_aperture()
110 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); in nbio_v6_1_enable_doorbell_selfring_aperture()
126 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v6_1_ih_doorbell_range()
134 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v6_1_ih_control()
142 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v6_1_ih_control()
Ddf_v1_7.c44 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); in df_v1_7_enable_broadcast_mode()
46 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, in df_v1_7_enable_broadcast_mode()
82 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
87 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); in df_v1_7_update_medium_grain_clock_gating()
Dsmu_v11_0_i2c.c58 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg); in smu_v11_0_i2c_set_clock_gating()
66 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0); in smu_v11_0_i2c_enable()
92 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg); in smu_v11_0_i2c_configure()
112 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2); in smu_v11_0_i2c_set_clock()
113 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120); in smu_v11_0_i2c_set_clock()
114 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130); in smu_v11_0_i2c_set_clock()
115 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20); in smu_v11_0_i2c_set_clock()
124 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF)); in smu_v11_0_i2c_set_address()
274 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); in smu_v11_0_i2c_transmit()
362 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); in smu_v11_0_i2c_receive()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmu9_smumgr.c86 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu9_send_msg_to_smc_without_waiting()
104 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc()
130 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter()
132 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu9_send_msg_to_smc_with_parameter()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_thermal.c142 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_static_mode()
145 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_static_mode()
162 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_default_mode()
166 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_fan_ctrl_set_default_mode()
278 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, in vega10_fan_ctrl_set_fan_speed_percent()
326 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, in vega10_fan_ctrl_set_fan_speed_rpm()
392 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); in vega10_thermal_set_temperature_range()
407 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, in vega10_thermal_initialize()
413 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega10_thermal_initialize()
447 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); in vega10_thermal_enable_alert()
[all …]
Dvega20_thermal.c94 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega20_fan_ctrl_set_static_mode()
97 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, in vega20_fan_ctrl_set_static_mode()
160 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, in vega20_fan_ctrl_set_fan_speed_percent()
203 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, in vega20_fan_ctrl_set_fan_speed_rpm()
266 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); in vega20_thermal_set_temperature_range()
285 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); in vega20_thermal_enable_alert()
298 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); in vega20_thermal_disable_alert()

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