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Searched refs:WREG32_SMC (Results 1 – 21 of 21) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Dtrinity_smc.c66 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
68 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
75 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
82 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
Dtrinity_dpm.c384 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
508 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()
526 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
531 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
535 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
539 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
600 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()
610 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); in trinity_set_divider_value()
622 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers()
634 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers()
[all …]
Dci_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
Dsi_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
Dci_dpm.c600 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
890 WREG32_SMC(CG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
897 WREG32_SMC(CG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
914 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
923 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
950 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
954 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1128 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
1205 WREG32_SMC(CG_TACH_CTRL, tmp);
1221 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
[all …]
Dkv_dpm.c277 WREG32_SMC(local_cac_reg->cntl, data);
317 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
408 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
409 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
412 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
413 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
416 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
417 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
420 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
421 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
[all …]
Dcik.c9443 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9490 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
9765 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
9771 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
9776 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
9781 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
9787 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
Dsi.c5466 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5467 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5478 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5479 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
Dradeon.h2529 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2563 WREG32_SMC(reg, tmp_); \
Dsi_dpm.c2766 WREG32_SMC(offset, data); in si_program_cac_config_registers()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dsi_smc.c117 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_start_smc()
131 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in amdgpu_si_reset_smc()
150 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_si_smc_clock()
Dkv_dpm.c403 WREG32_SMC(local_cac_reg->cntl, data);
443 WREG32_SMC(config_regs->offset, data); in kv_program_pt_config_registers()
534 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
535 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
538 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
539 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
542 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
543 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
546 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
547 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
[all …]
Dcik.c921 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
932 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1322 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1371 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1657 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1665 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1670 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1675 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1681 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
Dvi.c405 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
416 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
746 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
836 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
1441 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
Damdgpu_cgs.c96 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
Damdgpu_debugfs.c444 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
Damdgpu.h1077 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro
Dvce_v4_0.c883 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
Dsi_dpm.c2865 WREG32_SMC(offset, data); in si_program_cac_config_registers()
7517 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7522 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7534 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7539 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
Duvd_v7_0.c1689 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
Dgfx_v8_0.c793 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); in gfx_v8_0_init_golden_registers()