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Searched refs:WREG32_NO_KIQ (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_ai.c142 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
307 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
360 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_rcv_irq()
Dmxgpu_vi.c325 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
348 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
359 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); in xgpu_vi_mailbox_trans_msg()
506 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_ack_irq()
536 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_rcv_irq()
Dvi.c91 WREG32_NO_KIQ(mmPCIE_INDEX, reg); in vi_pcie_rreg()
103 WREG32_NO_KIQ(mmPCIE_INDEX, reg); in vi_pcie_wreg()
105 WREG32_NO_KIQ(mmPCIE_DATA, v); in vi_pcie_wreg()
116 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_rreg()
127 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_wreg()
128 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); in vi_smc_wreg()
Damdgpu_discovery.c144 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); in amdgpu_discovery_read_binary()
145 WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31); in amdgpu_discovery_read_binary()
Damdgpu_ttm.c1564 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000); in amdgpu_ttm_access_memory()
1565 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31); in amdgpu_ttm_access_memory()
1571 WREG32_NO_KIQ(mmMM_DATA, value); in amdgpu_ttm_access_memory()
2216 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); in amdgpu_ttm_vram_read()
2217 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); in amdgpu_ttm_vram_read()
2264 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000); in amdgpu_ttm_vram_write()
2265 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31); in amdgpu_ttm_vram_write()
2266 WREG32_NO_KIQ(mmMM_DATA, value); in amdgpu_ttm_vram_write()
Dsoc15_common.h45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
Dnbio_v7_0.c67 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); in nbio_v7_0_hdp_flush()
Dnbio_v7_4.c84 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); in nbio_v7_4_hdp_flush()
Dnavi10_ih.c239 WREG32_NO_KIQ(reg, tmp); in navi10_ih_get_wptr()
Dvega10_ih.c421 WREG32_NO_KIQ(reg, tmp); in vega10_ih_get_wptr()
Dgmc_v10_0.c238 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); in gmc_v10_0_flush_vm_hub()
Dgmc_v9_0.c494 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); in gmc_v9_0_flush_gpu_tlb()
Damdgpu.h1058 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) macro