Searched refs:WL (Results 1 – 15 of 15) sorted by relevance
38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local58 WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; in nvkm_gddr5_calc()70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()78 ram->mr[0] |= (WL & 0x07) << 0; in nvkm_gddr5_calc()
25 Ovislink AirLive WL-1120PCM26 Mentor WL-PCI36 Planet WL-355342 PheeNet WL-11PCIR44 Planet WL-8303
3 #define LOCK WL12 #define WLOCK WL
12 #define WLOCK WL
217 #define WL(x) write_lock(&rwlock_##x) macro219 #define WLU(x) WL(x); WU(x)345 WL(X2); // this one should fail in rlock_AA2()356 WL(X1); in rlock_AA3()380 WL(X1); in rlock_ABBA1()439 WL(X1); in rlock_ABBA3()445 WL(X1); in rlock_ABBA3()950 WL(A); \1000 WL(A); \1039 WL(A); \
30 Fiberline FL-WL-200X
64 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */135 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */
91 reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
155 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
128 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
120 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
18 and XL (with LEDs and OLEDs), Intuos 4 WL, Intuos 5 (LEDs only),
204 bool "Keith und Koep Trizeps4-WL DIMM-Module"
