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Searched refs:VCS1 (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dmmio_context.c126 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
154 [VCS1] = 0xca00,
341 [VCS1] = 0x4268,
401 [VCS1] = 0xca00, in switch_mocs()
Dexeclist.c53 [VCS1] = VCS2_AS_CONTEXT_SWITCH,
Dinterrupt.c539 if (HAS_ENGINE(gvt->dev_priv, VCS1)) { in gen8_init_irq()
Dcmd_parser.c412 #define R_VCS2 BIT(VCS1)
624 [VCS1] = {
1096 [VCS1] = {
Dhandlers.c342 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
1762 id = VCS1; in gvt_reg_tlb_control_handler()
1840 if (HAS_ENGINE(dev_priv, VCS1)) \
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_pci.c557 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
616 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
690 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
711 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_engine_types.h143 VCS1, enumerator
Dintel_mocs.c337 case VCS1: in mocs_register()
Dintel_reset.c290 [VCS1] = GEN8_GRDOM_MEDIA2, in gen6_reset_engines()
413 [VCS1] = GEN11_GRDOM_MEDIA2, in gen11_reset_engines()
Dintel_engine_cs.c97 [VCS1] = {
Dintel_lrc.c3058 [VCS1] = GEN8_VCS1_IRQ_SHIFT, in logical_ring_default_irqs()