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Searched refs:VCS0 (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/
Di915_pci.c324 .engine_mask = BIT(RCS0) | BIT(VCS0),
334 .engine_mask = BIT(RCS0) | BIT(VCS0),
342 .engine_mask = BIT(RCS0) | BIT(VCS0), \
369 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
417 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
483 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
493 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
557 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
566 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
616 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
[all …]
Di915_drv.h2076 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
Di915_gpu_error.c1121 case VCS0: in error_record_engine_registers()
Di915_irq.c4294 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]); in i965_irq_handler()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_engine_types.h142 VCS0, enumerator
146 #define _VCS(n) (VCS0 + (n))
Dintel_engine_user.c158 [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS }, in legacy_ring_idx()
Dintel_mocs.c331 case VCS0: in mocs_register()
Dintel_reset.c289 [VCS0] = GEN6_GRDOM_MEDIA, in gen6_reset_engines()
412 [VCS0] = GEN11_GRDOM_MEDIA, in gen11_reset_engines()
Dintel_engine_cs.c87 [VCS0] = {
Dintel_ringbuffer.c555 case VCS0: in set_hwsp()
Dintel_lrc.c3057 [VCS0] = GEN8_VCS0_IRQ_SHIFT, in logical_ring_default_irqs()
/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dmmio_context.c153 [VCS0] = 0xc900,
340 [VCS0] = 0x4264,
400 [VCS0] = 0xc900, in switch_mocs()
Dexeclist.c52 [VCS0] = VCS_AS_CONTEXT_SWITCH,
Dcmd_parser.c411 #define R_VCS1 BIT(VCS0)
591 [VCS0] = {
1091 [VCS0] = {
Dhandlers.c330 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
1759 id = VCS0; in gvt_reg_tlb_control_handler()
/Linux-v5.4/drivers/gpu/drm/i915/gem/
Di915_gem_execbuffer.c2108 GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0)); in num_vcs_engines()
2133 [I915_EXEC_BSD] = VCS0,