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Searched refs:VC4_SET_FIELD (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/vc4/
Dvc4_dsi.c871 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
872 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_encoder_enable()
883 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | in vc4_dsi_encoder_enable()
884 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | in vc4_dsi_encoder_enable()
885 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); in vc4_dsi_encoder_enable()
887 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
888 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_encoder_enable()
889 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | in vc4_dsi_encoder_enable()
890 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | in vc4_dsi_encoder_enable()
891 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | in vc4_dsi_encoder_enable()
[all …]
Dvc4_plane.c406 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | in vc4_write_tpz()
407 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); in vc4_write_tpz()
409 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); in vc4_write_tpz()
418 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | in vc4_write_ppf()
419 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); in vc4_write_ppf()
637 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); in vc4_plane_mode_set()
700 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | in vc4_plane_mode_set()
701 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | in vc4_plane_mode_set()
702 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | in vc4_plane_mode_set()
703 VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); in vc4_plane_mode_set()
[all …]
Dvc4_hdmi.c481 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_hdmi_encoder_enable()
483 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_hdmi_encoder_enable()
485 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); in vc4_hdmi_encoder_enable()
486 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_encoder_enable()
487 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, in vc4_hdmi_encoder_enable()
489 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_encoder_enable()
490 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_hdmi_encoder_enable()
548 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_encoder_enable()
552 VC4_SET_FIELD((mode->htotal - in vc4_hdmi_encoder_enable()
555 VC4_SET_FIELD((mode->hsync_end - in vc4_hdmi_encoder_enable()
[all …]
Dvc4_kms.c121 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
123 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
125 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
128 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
130 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
132 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
135 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
137 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
139 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
144 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); in vc4_ctm_commit()
Dvc4_crtc.c312 VC4_SET_FIELD((mode->htotal - in vc4_crtc_config_pv()
315 VC4_SET_FIELD((mode->hsync_end - in vc4_crtc_config_pv()
319 VC4_SET_FIELD((mode->hsync_start - in vc4_crtc_config_pv()
322 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); in vc4_crtc_config_pv()
325 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, in vc4_crtc_config_pv()
327 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_crtc_config_pv()
330 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_crtc_config_pv()
332 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
336 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_crtc_config_pv()
339 VC4_SET_FIELD(mode->crtc_vsync_end - in vc4_crtc_config_pv()
[all …]
Dvc4_dpi.c159 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
163 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
165 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
168 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
172 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
176 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, in vc4_dpi_encoder_enable()
185 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); in vc4_dpi_encoder_enable()
Dvc4_txp.c289 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
290 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
299 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
300 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
Dvc4_gem.c441 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
442 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
443 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
444 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
456 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
457 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
Dvc4_hvs.c296 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); in vc4_hvs_bind()
Dvc4_validate.c409 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
411 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
Dvc4_regs.h13 #define VC4_SET_FIELD(value, field) \ macro