Home
last modified time | relevance | path

Searched refs:UVD_RBC_RB_CNTL (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c394 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
395 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v5_0_start()
396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in uvd_v5_0_start()
397 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); in uvd_v5_0_start()
398 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v5_0_start()
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in uvd_v5_0_start()
Duvd_v6_0.c812 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
813 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v6_0_start()
814 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in uvd_v6_0_start()
815 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); in uvd_v6_0_start()
816 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v6_0_start()
817 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in uvd_v6_0_start()
838 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); in uvd_v6_0_start()
Dvcn_v2_0.c1022 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
1023 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start_dpg_mode()
1024 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in vcn_v2_0_start_dpg_mode()
1025 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in vcn_v2_0_start_dpg_mode()
1026 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in vcn_v2_0_start_dpg_mode()
1187 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
1188 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_0_start()
1189 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in vcn_v2_0_start()
1190 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in vcn_v2_0_start()
1191 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in vcn_v2_0_start()
Dvcn_v1_0.c905 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
906 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v1_0_start_spg_mode()
907 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in vcn_v1_0_start_spg_mode()
908 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in vcn_v1_0_start_spg_mode()
909 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in vcn_v1_0_start_spg_mode()
1078 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
1079 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v1_0_start_dpg_mode()
1080 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in vcn_v1_0_start_dpg_mode()
1081 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in vcn_v1_0_start_dpg_mode()
1082 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in vcn_v1_0_start_dpg_mode()
Duvd_v7_0.c895 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); in uvd_v7_0_sriov_start()
896 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in uvd_v7_0_sriov_start()
1062 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v7_0_start()
1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v7_0_start()
1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in uvd_v7_0_start()
1065 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); in uvd_v7_0_start()
1066 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in uvd_v7_0_start()
1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in uvd_v7_0_start()
Dvcn_v2_5.c850 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
851 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in vcn_v2_5_start()
852 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); in vcn_v2_5_start()
853 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); in vcn_v2_5_start()
854 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); in vcn_v2_5_start()
/Linux-v5.4/drivers/gpu/drm/radeon/
Duvd_v1_0.c358 WREG32(UVD_RBC_RB_CNTL, 0x11010101); in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
394 WREG32(UVD_RBC_RB_CNTL, 0x11010101); in uvd_v1_0_stop()
Dr600d.h1546 #define UVD_RBC_RB_CNTL 0xf6a4 macro