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Searched refs:UVD_MPC_SET_MUX__SET_1__SHIFT (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h635 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Duvd_4_0_sh_mask.h531 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003 macro
Duvd_4_2_sh_mask.h516 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
Duvd_5_0_sh_mask.h548 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
Duvd_6_0_sh_mask.h550 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1142 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_2_5_sh_mask.h2883 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2648 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c991 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_0_start_dpg_mode()
1119 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_0_start()
Dvcn_v1_0.c837 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v1_0_start_spg_mode()
1035 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
Dvcn_v2_5.c777 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | in vcn_v2_5_start()