Searched refs:UTMIP_PLL_CFG1 (Results 1 – 3 of 3) sorted by relevance
79 #define UTMIP_PLL_CFG1 0x804 macro496 val = readl(base + UTMIP_PLL_CFG1); in utmi_phy_power_on()501 writel(val, base + UTMIP_PLL_CFG1); in utmi_phy_power_on()
183 #define UTMIP_PLL_CFG1 0x484 macro1128 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()1138 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()1756 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1767 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1776 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()1779 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
168 #define UTMIP_PLL_CFG1 0x484 macro2767 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2778 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2781 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2784 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2799 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
