Searched refs:UTMIPLL_HW_PWRDN_CFG0 (Results 1 – 2 of 2) sorted by relevance
195 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro2710 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()2718 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()2726 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()2728 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()2748 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2750 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2804 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2807 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()2818 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()[all …]
205 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro1770 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1774 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1787 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1790 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1795 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()1797 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
