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Searched refs:UIC_ARG_MIB_SEL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/scsi/ufs/
Dtc-dwc-g210.c34 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
36 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
38 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14, in tc_dwc_g210_setup_40bit_rmmi()
40 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6, in tc_dwc_g210_setup_40bit_rmmi()
42 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01, in tc_dwc_g210_setup_40bit_rmmi()
44 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19, in tc_dwc_g210_setup_40bit_rmmi()
46 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4, in tc_dwc_g210_setup_40bit_rmmi()
48 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
52 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80, in tc_dwc_g210_setup_40bit_rmmi()
54 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03, in tc_dwc_g210_setup_40bit_rmmi()
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Dufs-hisi.c31 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
34 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
48 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
51 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 1), &tx_fsm_val_1); in ufs_hisi_check_hibern8()
146 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD0C1, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
148 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x156A, 0x0), 0x2); in ufs_hisi_link_startup_pre_change()
150 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
152 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D); in ufs_hisi_link_startup_pre_change()
154 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1); in ufs_hisi_link_startup_pre_change()
158 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98); in ufs_hisi_link_startup_pre_change()
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Dufshci.h258 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ macro
260 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
Dufs-qcom.c208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, in ufs_qcom_check_hibern8()
Dufshcd.c3830 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); in ufshcd_uic_change_pwr_mode()
4337 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
4342 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, in ufshcd_disable_tx_lcc()
6586 UIC_ARG_MIB_SEL( in ufshcd_tune_pa_tactivate()
6622 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()
6629 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, in ufshcd_tune_pa_hibern8time()