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Searched refs:UIC_ARG_MIB (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/drivers/scsi/ufs/
Dufshcd-dwc.c58 ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result); in ufshcd_dwc_link_is_up()
84 { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL }, in ufshcd_dwc_connection_setup()
85 { UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL }, in ufshcd_dwc_connection_setup()
86 { UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL }, in ufshcd_dwc_connection_setup()
87 { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL }, in ufshcd_dwc_connection_setup()
88 { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL }, in ufshcd_dwc_connection_setup()
89 { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL }, in ufshcd_dwc_connection_setup()
90 { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL }, in ufshcd_dwc_connection_setup()
91 { UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL }, in ufshcd_dwc_connection_setup()
92 { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL }, in ufshcd_dwc_connection_setup()
[all …]
Dtc-dwc-g210.c27 { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
28 { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
29 { UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
30 { UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
31 { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
32 { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
33 { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
50 { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
51 { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
74 { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL }, in tc_dwc_g210_setup_40bit_rmmi()
[all …]
Dufs-hisi.c255 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0); in ufs_hisi_link_startup_post_change()
257 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0); in ufs_hisi_link_startup_post_change()
259 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9); in ufs_hisi_link_startup_post_change()
268 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09a), 0x80000000); in ufs_hisi_link_startup_post_change()
270 ufshcd_dme_set(hba, UIC_ARG_MIB(0xd09c), 0x00000005); in ufs_hisi_link_startup_post_change()
320 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13); in ufs_hisi_pwr_change_pre_change()
322 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f); in ufs_hisi_pwr_change_pre_change()
324 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f); in ufs_hisi_pwr_change_pre_change()
326 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f); in ufs_hisi_pwr_change_pre_change()
328 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA); in ufs_hisi_pwr_change_pre_change()
[all …]
Dufs-mediatek.c25 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp); in ufs_mtk_cfg_unipro_cg()
31 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp); in ufs_mtk_cfg_unipro_cg()
34 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp); in ufs_mtk_cfg_unipro_cg()
37 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp); in ufs_mtk_cfg_unipro_cg()
40 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp); in ufs_mtk_cfg_unipro_cg()
45 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp); in ufs_mtk_cfg_unipro_cg()
48 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp); in ufs_mtk_cfg_unipro_cg()
51 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp); in ufs_mtk_cfg_unipro_cg()
227 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp); in ufs_mtk_pre_link()
233 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp); in ufs_mtk_pre_link()
[all …]
Dufs-qcom.c62 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes); in ufs_qcom_get_connected_tx_lanes()
514 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), in ufs_qcom_link_startup_notify()
895 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
901 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
1229 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1241 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1274 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), in ufs_qcom_clk_scale_down_pre_change()
1282 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), in ufs_qcom_clk_scale_down_pre_change()
Dcdns-pltfrm.c100 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); in cdns_ufs_link_startup_notify()
Dufshcd-pci.c42 u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE); in ufs_intel_disable_lcc()
Dufshcd.c3839 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); in ufshcd_uic_change_pwr_mode()
3988 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), in ufshcd_get_max_pwr_mode()
3990 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), in ufshcd_get_max_pwr_mode()
4006 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); in ufshcd_get_max_pwr_mode()
4008 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), in ufshcd_get_max_pwr_mode()
4018 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), in ufshcd_get_max_pwr_mode()
4021 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), in ufshcd_get_max_pwr_mode()
4058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); in ufshcd_change_power_mode()
4059 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), in ufshcd_change_power_mode()
4063 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); in ufshcd_change_power_mode()
[all …]
Dufshci.h260 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) macro