1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef UFS_QCOM_PHY_QMP_20NM_H_ 7 #define UFS_QCOM_PHY_QMP_20NM_H_ 8 9 #include "phy-qcom-ufs-i.h" 10 11 /* QCOM UFS PHY control registers */ 12 13 #define COM_OFF(x) (0x000 + x) 14 #define PHY_OFF(x) (0xC00 + x) 15 #define TX_OFF(n, x) (0x400 + (0x400 * n) + x) 16 #define RX_OFF(n, x) (0x600 + (0x400 * n) + x) 17 18 /* UFS PHY PLL block registers */ 19 #define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x0) 20 #define QSERDES_COM_PLL_VCOTAIL_EN COM_OFF(0x04) 21 #define QSERDES_COM_PLL_CNTRL COM_OFF(0x14) 22 #define QSERDES_COM_PLL_IP_SETI COM_OFF(0x24) 23 #define QSERDES_COM_CORE_CLK_IN_SYNC_SEL COM_OFF(0x28) 24 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x30) 25 #define QSERDES_COM_PLL_CP_SETI COM_OFF(0x34) 26 #define QSERDES_COM_PLL_IP_SETP COM_OFF(0x38) 27 #define QSERDES_COM_PLL_CP_SETP COM_OFF(0x3C) 28 #define QSERDES_COM_SYSCLK_EN_SEL_TXBAND COM_OFF(0x48) 29 #define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x4C) 30 #define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x50) 31 #define QSERDES_COM_PLLLOCK_CMP1 COM_OFF(0x90) 32 #define QSERDES_COM_PLLLOCK_CMP2 COM_OFF(0x94) 33 #define QSERDES_COM_PLLLOCK_CMP3 COM_OFF(0x98) 34 #define QSERDES_COM_PLLLOCK_CMP_EN COM_OFF(0x9C) 35 #define QSERDES_COM_BGTC COM_OFF(0xA0) 36 #define QSERDES_COM_DEC_START1 COM_OFF(0xAC) 37 #define QSERDES_COM_PLL_AMP_OS COM_OFF(0xB0) 38 #define QSERDES_COM_RES_CODE_UP_OFFSET COM_OFF(0xD8) 39 #define QSERDES_COM_RES_CODE_DN_OFFSET COM_OFF(0xDC) 40 #define QSERDES_COM_DIV_FRAC_START1 COM_OFF(0x100) 41 #define QSERDES_COM_DIV_FRAC_START2 COM_OFF(0x104) 42 #define QSERDES_COM_DIV_FRAC_START3 COM_OFF(0x108) 43 #define QSERDES_COM_DEC_START2 COM_OFF(0x10C) 44 #define QSERDES_COM_PLL_RXTXEPCLK_EN COM_OFF(0x110) 45 #define QSERDES_COM_PLL_CRCTRL COM_OFF(0x114) 46 #define QSERDES_COM_PLL_CLKEPDIV COM_OFF(0x118) 47 48 /* TX LANE n (0, 1) registers */ 49 #define QSERDES_TX_EMP_POST1_LVL(n) TX_OFF(n, 0x08) 50 #define QSERDES_TX_DRV_LVL(n) TX_OFF(n, 0x0C) 51 #define QSERDES_TX_LANE_MODE(n) TX_OFF(n, 0x54) 52 53 /* RX LANE n (0, 1) registers */ 54 #define QSERDES_RX_CDR_CONTROL1(n) RX_OFF(n, 0x0) 55 #define QSERDES_RX_CDR_CONTROL_HALF(n) RX_OFF(n, 0x8) 56 #define QSERDES_RX_RX_EQ_GAIN1_LSB(n) RX_OFF(n, 0xA8) 57 #define QSERDES_RX_RX_EQ_GAIN1_MSB(n) RX_OFF(n, 0xAC) 58 #define QSERDES_RX_RX_EQ_GAIN2_LSB(n) RX_OFF(n, 0xB0) 59 #define QSERDES_RX_RX_EQ_GAIN2_MSB(n) RX_OFF(n, 0xB4) 60 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(n) RX_OFF(n, 0xBC) 61 #define QSERDES_RX_CDR_CONTROL_QUARTER(n) RX_OFF(n, 0xC) 62 #define QSERDES_RX_SIGDET_CNTRL(n) RX_OFF(n, 0x100) 63 64 /* UFS PHY registers */ 65 #define UFS_PHY_PHY_START PHY_OFF(0x00) 66 #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x4) 67 #define UFS_PHY_TX_LANE_ENABLE PHY_OFF(0x44) 68 #define UFS_PHY_PWM_G1_CLK_DIVIDER PHY_OFF(0x08) 69 #define UFS_PHY_PWM_G2_CLK_DIVIDER PHY_OFF(0x0C) 70 #define UFS_PHY_PWM_G3_CLK_DIVIDER PHY_OFF(0x10) 71 #define UFS_PHY_PWM_G4_CLK_DIVIDER PHY_OFF(0x14) 72 #define UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER PHY_OFF(0x34) 73 #define UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER PHY_OFF(0x38) 74 #define UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER PHY_OFF(0x3C) 75 #define UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER PHY_OFF(0x40) 76 #define UFS_PHY_OMC_STATUS_RDVAL PHY_OFF(0x68) 77 #define UFS_PHY_LINE_RESET_TIME PHY_OFF(0x28) 78 #define UFS_PHY_LINE_RESET_GRANULARITY PHY_OFF(0x2C) 79 #define UFS_PHY_TSYNC_RSYNC_CNTL PHY_OFF(0x48) 80 #define UFS_PHY_PLL_CNTL PHY_OFF(0x50) 81 #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x54) 82 #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x5C) 83 #define UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL PHY_OFF(0x58) 84 #define UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL PHY_OFF(0x60) 85 #define UFS_PHY_CFG_CHANGE_CNT_VAL PHY_OFF(0x64) 86 #define UFS_PHY_RX_SYNC_WAIT_TIME PHY_OFF(0x6C) 87 #define UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB4) 88 #define UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE0) 89 #define UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xB8) 90 #define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY PHY_OFF(0xE4) 91 #define UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xBC) 92 #define UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY PHY_OFF(0xE8) 93 #define UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY PHY_OFF(0xFC) 94 #define UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY PHY_OFF(0x100) 95 #define UFS_PHY_RX_SIGDET_CTRL3 PHY_OFF(0x14c) 96 #define UFS_PHY_RMMI_ATTR_CTRL PHY_OFF(0x160) 97 #define UFS_PHY_RMMI_RX_CFGUPDT_L1 (1 << 7) 98 #define UFS_PHY_RMMI_TX_CFGUPDT_L1 (1 << 6) 99 #define UFS_PHY_RMMI_CFGWR_L1 (1 << 5) 100 #define UFS_PHY_RMMI_CFGRD_L1 (1 << 4) 101 #define UFS_PHY_RMMI_RX_CFGUPDT_L0 (1 << 3) 102 #define UFS_PHY_RMMI_TX_CFGUPDT_L0 (1 << 2) 103 #define UFS_PHY_RMMI_CFGWR_L0 (1 << 1) 104 #define UFS_PHY_RMMI_CFGRD_L0 (1 << 0) 105 #define UFS_PHY_RMMI_ATTRID PHY_OFF(0x164) 106 #define UFS_PHY_RMMI_ATTRWRVAL PHY_OFF(0x168) 107 #define UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS PHY_OFF(0x16C) 108 #define UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS PHY_OFF(0x170) 109 #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x174) 110 111 #define UFS_PHY_TX_LANE_ENABLE_MASK 0x3 112 113 /* 114 * This structure represents the 20nm specific phy. 115 * common_cfg MUST remain the first field in this structure 116 * in case extra fields are added. This way, when calling 117 * get_ufs_qcom_phy() of generic phy, we can extract the 118 * common phy structure (struct ufs_qcom_phy) out of it 119 * regardless of the relevant specific phy. 120 */ 121 struct ufs_qcom_phy_qmp_20nm { 122 struct ufs_qcom_phy common_cfg; 123 }; 124 125 static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_2_0[] = { 126 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), 127 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D), 128 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1), 129 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc), 130 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08), 131 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03), 132 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10), 133 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82), 134 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03), 135 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80), 136 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80), 137 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40), 138 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff), 139 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19), 140 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00), 141 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03), 142 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90), 143 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03), 144 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2), 145 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c), 146 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12), 147 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2), 148 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c), 149 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12), 150 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff), 151 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff), 152 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff), 153 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00), 154 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff), 155 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff), 156 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff), 157 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00), 158 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f), 159 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b), 160 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f), 161 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01), 162 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F), 163 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20), 164 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F), 165 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20), 166 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68), 167 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68), 168 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc), 169 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc), 170 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3), 171 }; 172 173 static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_1_3_0[] = { 174 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), 175 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL3, 0x0D), 176 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1), 177 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc), 178 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08), 179 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03), 180 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10), 181 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82), 182 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03), 183 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80), 184 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80), 185 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40), 186 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff), 187 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19), 188 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00), 189 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03), 190 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90), 191 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03), 192 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2), 193 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c), 194 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12), 195 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2), 196 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c), 197 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12), 198 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff), 199 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff), 200 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff), 201 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00), 202 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff), 203 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff), 204 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff), 205 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00), 206 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x2b), 207 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x38), 208 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x3c), 209 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_UP_OFFSET, 0x02), 210 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RES_CODE_DN_OFFSET, 0x02), 211 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01), 212 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CNTRL, 0x40), 213 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68), 214 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68), 215 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc), 216 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc), 217 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3), 218 }; 219 220 static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { 221 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98), 222 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65), 223 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e), 224 }; 225 226 #endif 227
