Searched refs:TEGRA210_CLK_PLL_C4_OUT0 (Results 1 – 3 of 3) sorted by relevance
340 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
1136 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,1138 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1199 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;1200 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
2464 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },2549 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },3223 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; in tegra210_pll_init()
