Searched refs:Stream (Results 1 – 25 of 46) sorted by relevance
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3 # "Xilinx AXI-Stream FIFO IP core driver"6 tristate "Xilinx AXI-Stream FIFO IP core driver"9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
1 Xilinx AXI-Stream FIFO v4.1 IP core3 This IP core has read and write AXI-Stream FIFOs, the contents of which can28 - xlnx,axis-tdest-width: AXI-Stream TDEST width29 - xlnx,axis-tid-width: AXI-Stream TID width30 - xlnx,axis-tuser-width: AXI-Stream TUSER width
16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)18 - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)19 - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)20 - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)21 - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
31 1 Stream 0 output32 2 Stream 1 output33 3 Stream 2 output34 4 Stream 3 output
31 1 Stream 0 input32 2 Stream 1 input33 3 Stream 2 input34 4 Stream 3 input
2 Audio Stream in SoundWire22 Stream Sample in memory (System memory, DSP memory or FIFOs) ::28 Example 1: Stereo Stream with L and R channels is rendered from Master to41 Example 2: Stereo Stream with L and R channels is captured from Slave to55 Example 3: Stereo Stream with L and R channels is rendered by Master. Each79 Example 4: Stereo Stream with L and R channel is rendered by two different104 Example 5: Stereo Stream with L and R channel is rendered by 2 Masters, each132 SoundWire Stream Management flow135 Stream definitions172 NOTE2: Stream state transition checks need to be handled by caller[all …]
24 - Access of Stream data structure.
38 5 - Voice Stream Manager Service.40 7 - Audio Stream Manager Service.
78 portion of every Stream ID (e.g. for certain MMU-500105 and their corresponding Stream IDs. Each device node107 property, indicating the number of Stream ID
60 Picking new Stream IDs to use63 Stream ID 0 is reserved, and should not be used to communicate with devices. If
16 Description: Default value for the Data Stream Control Register (DSCR) on
45 Dynamic Stream Compression support
22 multiplexed using MPEG Transport Stream [#f1]_.
334 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */ member560 u8 Stream; member664 u8 Stream; member
1 Qualcomm Audio Stream Manager (Q6ASM) binding
6 SCTP (Stream Control Transmission Protocol) is a IP based, message oriented,
44 Stream domain137 Stream Domain Widgets140 Stream Widgets relate to the stream power domain and only consist of ADCs144 Stream widgets have the following format:-
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
46 digitally recorded Transport Stream. Matching filters have to be defined
44 Elementary Stream (PES) data. The filtered data is transferred from
70 A recorded Transport Stream is replayed by writing to this device.
254 - Kworld/Tevion V-Stream Xpert TV PVR7134278 - V-Stream Studio TV Terminator
416 MPEG Stream Embedded, Sliced VBI Data Format: NONE428 MPEG Stream Embedded, Sliced VBI Data Format: IVTV435 Stream 1 PES* packet encapsulated in an MPEG-2 *Program Pack* in the454 Stream 1 PES* packets that contain sliced VBI data when456 is set. (The MPEG-2 *Private Stream 1 PES* packet header and460 The payload of the MPEG-2 *Private Stream 1 PES* packets that contain
15 Stream Control Transmission Protocol
628 between memory and AXI4-Stream video type target630 Stream Video Protocol. It has two stream interfaces/631 channels, Memory Mapped to Stream (MM2S) and Stream to637 memory access between memory and AXI4-Stream target peripherals.
