1 /*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define IDM_CTRL_DIRECT_OFFSET 0x00
25 #define CFG_OFFSET 0x00
26 #define CFG_RESET_SHIFT 31
27 #define CFG_EN_SHIFT 30
28 #define CFG_SLAVE_ADDR_0_SHIFT 28
29 #define CFG_M_RETRY_CNT_SHIFT 16
30 #define CFG_M_RETRY_CNT_MASK 0x0f
31
32 #define TIM_CFG_OFFSET 0x04
33 #define TIM_CFG_MODE_400_SHIFT 31
34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24
35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
38
39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08
40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24
42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16
45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8
48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0
51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
52
53 #define M_FIFO_CTRL_OFFSET 0x0c
54 #define M_FIFO_RX_FLUSH_SHIFT 31
55 #define M_FIFO_TX_FLUSH_SHIFT 30
56 #define M_FIFO_RX_CNT_SHIFT 16
57 #define M_FIFO_RX_CNT_MASK 0x7f
58 #define M_FIFO_RX_THLD_SHIFT 8
59 #define M_FIFO_RX_THLD_MASK 0x3f
60
61 #define S_FIFO_CTRL_OFFSET 0x10
62 #define S_FIFO_RX_FLUSH_SHIFT 31
63 #define S_FIFO_TX_FLUSH_SHIFT 30
64 #define S_FIFO_RX_CNT_SHIFT 16
65 #define S_FIFO_RX_CNT_MASK 0x7f
66 #define S_FIFO_RX_THLD_SHIFT 8
67 #define S_FIFO_RX_THLD_MASK 0x3f
68
69 #define M_CMD_OFFSET 0x30
70 #define M_CMD_START_BUSY_SHIFT 31
71 #define M_CMD_STATUS_SHIFT 25
72 #define M_CMD_STATUS_MASK 0x07
73 #define M_CMD_STATUS_SUCCESS 0x0
74 #define M_CMD_STATUS_LOST_ARB 0x1
75 #define M_CMD_STATUS_NACK_ADDR 0x2
76 #define M_CMD_STATUS_NACK_DATA 0x3
77 #define M_CMD_STATUS_TIMEOUT 0x4
78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5
79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6
80 #define M_CMD_PROTOCOL_SHIFT 9
81 #define M_CMD_PROTOCOL_MASK 0xf
82 #define M_CMD_PROTOCOL_BLK_WR 0x7
83 #define M_CMD_PROTOCOL_BLK_RD 0x8
84 #define M_CMD_PEC_SHIFT 8
85 #define M_CMD_RD_CNT_SHIFT 0
86 #define M_CMD_RD_CNT_MASK 0xff
87
88 #define S_CMD_OFFSET 0x34
89 #define S_CMD_START_BUSY_SHIFT 31
90 #define S_CMD_STATUS_SHIFT 23
91 #define S_CMD_STATUS_MASK 0x07
92 #define S_CMD_STATUS_SUCCESS 0x0
93 #define S_CMD_STATUS_TIMEOUT 0x5
94
95 #define IE_OFFSET 0x38
96 #define IE_M_RX_FIFO_FULL_SHIFT 31
97 #define IE_M_RX_THLD_SHIFT 30
98 #define IE_M_START_BUSY_SHIFT 28
99 #define IE_M_TX_UNDERRUN_SHIFT 27
100 #define IE_S_RX_FIFO_FULL_SHIFT 26
101 #define IE_S_RX_THLD_SHIFT 25
102 #define IE_S_RX_EVENT_SHIFT 24
103 #define IE_S_START_BUSY_SHIFT 23
104 #define IE_S_TX_UNDERRUN_SHIFT 22
105 #define IE_S_RD_EVENT_SHIFT 21
106
107 #define IS_OFFSET 0x3c
108 #define IS_M_RX_FIFO_FULL_SHIFT 31
109 #define IS_M_RX_THLD_SHIFT 30
110 #define IS_M_START_BUSY_SHIFT 28
111 #define IS_M_TX_UNDERRUN_SHIFT 27
112 #define IS_S_RX_FIFO_FULL_SHIFT 26
113 #define IS_S_RX_THLD_SHIFT 25
114 #define IS_S_RX_EVENT_SHIFT 24
115 #define IS_S_START_BUSY_SHIFT 23
116 #define IS_S_TX_UNDERRUN_SHIFT 22
117 #define IS_S_RD_EVENT_SHIFT 21
118
119 #define M_TX_OFFSET 0x40
120 #define M_TX_WR_STATUS_SHIFT 31
121 #define M_TX_DATA_SHIFT 0
122 #define M_TX_DATA_MASK 0xff
123
124 #define M_RX_OFFSET 0x44
125 #define M_RX_STATUS_SHIFT 30
126 #define M_RX_STATUS_MASK 0x03
127 #define M_RX_PEC_ERR_SHIFT 29
128 #define M_RX_DATA_SHIFT 0
129 #define M_RX_DATA_MASK 0xff
130
131 #define S_TX_OFFSET 0x48
132 #define S_TX_WR_STATUS_SHIFT 31
133 #define S_TX_DATA_SHIFT 0
134 #define S_TX_DATA_MASK 0xff
135
136 #define S_RX_OFFSET 0x4c
137 #define S_RX_STATUS_SHIFT 30
138 #define S_RX_STATUS_MASK 0x03
139 #define S_RX_PEC_ERR_SHIFT 29
140 #define S_RX_DATA_SHIFT 0
141 #define S_RX_DATA_MASK 0xff
142
143 #define I2C_TIMEOUT_MSEC 50000
144 #define M_TX_RX_FIFO_SIZE 64
145 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
146
147 #define M_RX_MAX_READ_LEN 255
148 #define M_RX_FIFO_THLD_VALUE 50
149
150 #define IE_M_ALL_INTERRUPT_SHIFT 27
151 #define IE_M_ALL_INTERRUPT_MASK 0x1e
152
153 #define SLAVE_READ_WRITE_BIT_MASK 0x1
154 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1
155 #define SLAVE_MAX_SIZE_TRANSACTION 64
156 #define SLAVE_CLOCK_STRETCH_TIME 25
157
158 #define IE_S_ALL_INTERRUPT_SHIFT 21
159 #define IE_S_ALL_INTERRUPT_MASK 0x3f
160
161 enum i2c_slave_read_status {
162 I2C_SLAVE_RX_FIFO_EMPTY = 0,
163 I2C_SLAVE_RX_START,
164 I2C_SLAVE_RX_DATA,
165 I2C_SLAVE_RX_END,
166 };
167
168 enum bus_speed_index {
169 I2C_SPD_100K = 0,
170 I2C_SPD_400K,
171 };
172
173 enum bcm_iproc_i2c_type {
174 IPROC_I2C,
175 IPROC_I2C_NIC
176 };
177
178 struct bcm_iproc_i2c_dev {
179 struct device *device;
180 enum bcm_iproc_i2c_type type;
181 int irq;
182
183 void __iomem *base;
184 void __iomem *idm_base;
185
186 u32 ape_addr_mask;
187
188 /* lock for indirect access through IDM */
189 spinlock_t idm_lock;
190
191 struct i2c_adapter adapter;
192 unsigned int bus_speed;
193
194 struct completion done;
195 int xfer_is_done;
196
197 struct i2c_msg *msg;
198
199 struct i2c_client *slave;
200
201 /* bytes that have been transferred */
202 unsigned int tx_bytes;
203 /* bytes that have been read */
204 unsigned int rx_bytes;
205 unsigned int thld_bytes;
206 };
207
208 /*
209 * Can be expanded in the future if more interrupt status bits are utilized
210 */
211 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
212 | BIT(IS_M_RX_THLD_SHIFT))
213
214 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
215 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
216 | BIT(IS_S_TX_UNDERRUN_SHIFT))
217
218 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
219 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
220 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
221 bool enable);
222
iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset)223 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
224 u32 offset)
225 {
226 u32 val;
227
228 if (iproc_i2c->idm_base) {
229 spin_lock(&iproc_i2c->idm_lock);
230 writel(iproc_i2c->ape_addr_mask,
231 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
232 val = readl(iproc_i2c->base + offset);
233 spin_unlock(&iproc_i2c->idm_lock);
234 } else {
235 val = readl(iproc_i2c->base + offset);
236 }
237
238 return val;
239 }
240
iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset,u32 val)241 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
242 u32 offset, u32 val)
243 {
244 if (iproc_i2c->idm_base) {
245 spin_lock(&iproc_i2c->idm_lock);
246 writel(iproc_i2c->ape_addr_mask,
247 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
248 writel(val, iproc_i2c->base + offset);
249 spin_unlock(&iproc_i2c->idm_lock);
250 } else {
251 writel(val, iproc_i2c->base + offset);
252 }
253 }
254
bcm_iproc_i2c_slave_init(struct bcm_iproc_i2c_dev * iproc_i2c,bool need_reset)255 static void bcm_iproc_i2c_slave_init(
256 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
257 {
258 u32 val;
259
260 if (need_reset) {
261 /* put controller in reset */
262 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
263 val |= BIT(CFG_RESET_SHIFT);
264 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
265
266 /* wait 100 usec per spec */
267 udelay(100);
268
269 /* bring controller out of reset */
270 val &= ~(BIT(CFG_RESET_SHIFT));
271 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
272 }
273
274 /* flush TX/RX FIFOs */
275 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
276 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
277
278 /* Maximum slave stretch time */
279 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
280 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
281 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
282 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
283
284 /* Configure the slave address */
285 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
286 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
287 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
288 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
289 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
290
291 /* clear all pending slave interrupts */
292 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
293
294 /* Enable interrupt register to indicate a valid byte in receive fifo */
295 val = BIT(IE_S_RX_EVENT_SHIFT);
296 /* Enable interrupt register for the Slave BUSY command */
297 val |= BIT(IE_S_START_BUSY_SHIFT);
298 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
299 }
300
bcm_iproc_i2c_check_slave_status(struct bcm_iproc_i2c_dev * iproc_i2c)301 static void bcm_iproc_i2c_check_slave_status(
302 struct bcm_iproc_i2c_dev *iproc_i2c)
303 {
304 u32 val;
305
306 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
307 /* status is valid only when START_BUSY is cleared after it was set */
308 if (val & BIT(S_CMD_START_BUSY_SHIFT))
309 return;
310
311 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
312 if (val == S_CMD_STATUS_TIMEOUT) {
313 dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
314
315 /* re-initialize i2c for recovery */
316 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
317 bcm_iproc_i2c_slave_init(iproc_i2c, true);
318 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
319 }
320 }
321
bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)322 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
323 u32 status)
324 {
325 u32 val;
326 u8 value, rx_status;
327
328 /* Slave RX byte receive */
329 if (status & BIT(IS_S_RX_EVENT_SHIFT)) {
330 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
331 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
332 if (rx_status == I2C_SLAVE_RX_START) {
333 /* Start of SMBUS for Master write */
334 i2c_slave_event(iproc_i2c->slave,
335 I2C_SLAVE_WRITE_REQUESTED, &value);
336
337 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
338 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
339 i2c_slave_event(iproc_i2c->slave,
340 I2C_SLAVE_WRITE_RECEIVED, &value);
341 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
342 /* Start of SMBUS for Master Read */
343 i2c_slave_event(iproc_i2c->slave,
344 I2C_SLAVE_READ_REQUESTED, &value);
345 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
346
347 val = BIT(S_CMD_START_BUSY_SHIFT);
348 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
349
350 /*
351 * Enable interrupt for TX FIFO becomes empty and
352 * less than PKT_LENGTH bytes were output on the SMBUS
353 */
354 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
355 val |= BIT(IE_S_TX_UNDERRUN_SHIFT);
356 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
357 } else {
358 /* Master write other than start */
359 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
360 i2c_slave_event(iproc_i2c->slave,
361 I2C_SLAVE_WRITE_RECEIVED, &value);
362 }
363 } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
364 /* Master read other than start */
365 i2c_slave_event(iproc_i2c->slave,
366 I2C_SLAVE_READ_PROCESSED, &value);
367
368 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
369 val = BIT(S_CMD_START_BUSY_SHIFT);
370 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
371 }
372
373 /* Stop */
374 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
375 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
376 /*
377 * Enable interrupt for TX FIFO becomes empty and
378 * less than PKT_LENGTH bytes were output on the SMBUS
379 */
380 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
381 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
382 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
383 }
384
385 /* clear interrupt status */
386 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
387
388 bcm_iproc_i2c_check_slave_status(iproc_i2c);
389 return true;
390 }
391
bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev * iproc_i2c)392 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
393 {
394 struct i2c_msg *msg = iproc_i2c->msg;
395 uint32_t val;
396
397 /* Read valid data from RX FIFO */
398 while (iproc_i2c->rx_bytes < msg->len) {
399 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
400
401 /* rx fifo empty */
402 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
403 break;
404
405 msg->buf[iproc_i2c->rx_bytes] =
406 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
407 iproc_i2c->rx_bytes++;
408 }
409 }
410
bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev * iproc_i2c)411 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
412 {
413 struct i2c_msg *msg = iproc_i2c->msg;
414 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
415 unsigned int i;
416 u32 val;
417
418 /* can only fill up to the FIFO size */
419 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
420 for (i = 0; i < tx_bytes; i++) {
421 /* start from where we left over */
422 unsigned int idx = iproc_i2c->tx_bytes + i;
423
424 val = msg->buf[idx];
425
426 /* mark the last byte */
427 if (idx == msg->len - 1) {
428 val |= BIT(M_TX_WR_STATUS_SHIFT);
429
430 if (iproc_i2c->irq) {
431 u32 tmp;
432
433 /*
434 * Since this is the last byte, we should now
435 * disable TX FIFO underrun interrupt
436 */
437 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
438 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
439 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
440 tmp);
441 }
442 }
443
444 /* load data into TX FIFO */
445 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
446 }
447
448 /* update number of transferred bytes */
449 iproc_i2c->tx_bytes += tx_bytes;
450 }
451
bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev * iproc_i2c)452 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
453 {
454 struct i2c_msg *msg = iproc_i2c->msg;
455 u32 bytes_left, val;
456
457 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
458 bytes_left = msg->len - iproc_i2c->rx_bytes;
459 if (bytes_left == 0) {
460 if (iproc_i2c->irq) {
461 /* finished reading all data, disable rx thld event */
462 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
463 val &= ~BIT(IS_M_RX_THLD_SHIFT);
464 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
465 }
466 } else if (bytes_left < iproc_i2c->thld_bytes) {
467 /* set bytes left as threshold */
468 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
469 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
470 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
471 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
472 iproc_i2c->thld_bytes = bytes_left;
473 }
474 /*
475 * bytes_left >= iproc_i2c->thld_bytes,
476 * hence no need to change the THRESHOLD SET.
477 * It will remain as iproc_i2c->thld_bytes itself
478 */
479 }
480
bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)481 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
482 u32 status)
483 {
484 /* TX FIFO is empty and we have more data to send */
485 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
486 bcm_iproc_i2c_send(iproc_i2c);
487
488 /* RX FIFO threshold is reached and data needs to be read out */
489 if (status & BIT(IS_M_RX_THLD_SHIFT))
490 bcm_iproc_i2c_read(iproc_i2c);
491
492 /* transfer is done */
493 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
494 iproc_i2c->xfer_is_done = 1;
495 if (iproc_i2c->irq)
496 complete(&iproc_i2c->done);
497 }
498 }
499
bcm_iproc_i2c_isr(int irq,void * data)500 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
501 {
502 struct bcm_iproc_i2c_dev *iproc_i2c = data;
503 u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
504 bool ret;
505 u32 sl_status = status & ISR_MASK_SLAVE;
506
507 if (sl_status) {
508 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
509 if (ret)
510 return IRQ_HANDLED;
511 else
512 return IRQ_NONE;
513 }
514
515 status &= ISR_MASK;
516 if (!status)
517 return IRQ_NONE;
518
519 /* process all master based events */
520 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
521 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
522
523 return IRQ_HANDLED;
524 }
525
bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev * iproc_i2c)526 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
527 {
528 u32 val;
529
530 /* put controller in reset */
531 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
532 val |= BIT(CFG_RESET_SHIFT);
533 val &= ~(BIT(CFG_EN_SHIFT));
534 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
535
536 /* wait 100 usec per spec */
537 udelay(100);
538
539 /* bring controller out of reset */
540 val &= ~(BIT(CFG_RESET_SHIFT));
541 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
542
543 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
544 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
545 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
546 /* disable all interrupts */
547 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
548 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
549 IE_M_ALL_INTERRUPT_SHIFT);
550 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
551
552 /* clear all pending interrupts */
553 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
554
555 return 0;
556 }
557
bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev * iproc_i2c,bool enable)558 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
559 bool enable)
560 {
561 u32 val;
562
563 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
564 if (enable)
565 val |= BIT(CFG_EN_SHIFT);
566 else
567 val &= ~BIT(CFG_EN_SHIFT);
568 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
569 }
570
bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg)571 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
572 struct i2c_msg *msg)
573 {
574 u32 val;
575
576 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
577 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
578
579 switch (val) {
580 case M_CMD_STATUS_SUCCESS:
581 return 0;
582
583 case M_CMD_STATUS_LOST_ARB:
584 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
585 return -EAGAIN;
586
587 case M_CMD_STATUS_NACK_ADDR:
588 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
589 return -ENXIO;
590
591 case M_CMD_STATUS_NACK_DATA:
592 dev_dbg(iproc_i2c->device, "NAK data\n");
593 return -ENXIO;
594
595 case M_CMD_STATUS_TIMEOUT:
596 dev_dbg(iproc_i2c->device, "bus timeout\n");
597 return -ETIMEDOUT;
598
599 case M_CMD_STATUS_FIFO_UNDERRUN:
600 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
601 return -ENXIO;
602
603 case M_CMD_STATUS_RX_FIFO_FULL:
604 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
605 return -ETIMEDOUT;
606
607 default:
608 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
609
610 /* re-initialize i2c for recovery */
611 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
612 bcm_iproc_i2c_init(iproc_i2c);
613 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
614
615 return -EIO;
616 }
617 }
618
bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg,u32 cmd)619 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
620 struct i2c_msg *msg,
621 u32 cmd)
622 {
623 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
624 u32 val, status;
625 int ret;
626
627 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
628
629 if (iproc_i2c->irq) {
630 time_left = wait_for_completion_timeout(&iproc_i2c->done,
631 time_left);
632 /* disable all interrupts */
633 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
634 /* read it back to flush the write */
635 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
636 /* make sure the interrupt handler isn't running */
637 synchronize_irq(iproc_i2c->irq);
638
639 } else { /* polling mode */
640 unsigned long timeout = jiffies + time_left;
641
642 do {
643 status = iproc_i2c_rd_reg(iproc_i2c,
644 IS_OFFSET) & ISR_MASK;
645 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
646 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
647
648 if (time_after(jiffies, timeout)) {
649 time_left = 0;
650 break;
651 }
652
653 cpu_relax();
654 cond_resched();
655 } while (!iproc_i2c->xfer_is_done);
656 }
657
658 if (!time_left && !iproc_i2c->xfer_is_done) {
659 dev_err(iproc_i2c->device, "transaction timed out\n");
660
661 /* flush both TX/RX FIFOs */
662 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
663 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
664 return -ETIMEDOUT;
665 }
666
667 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
668 if (ret) {
669 /* flush both TX/RX FIFOs */
670 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
671 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
672 return ret;
673 }
674
675 return 0;
676 }
677
bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg)678 static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
679 struct i2c_msg *msg)
680 {
681 int i;
682 u8 addr;
683 u32 val, tmp, val_intr_en;
684 unsigned int tx_bytes;
685
686 /* check if bus is busy */
687 if (!!(iproc_i2c_rd_reg(iproc_i2c,
688 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
689 dev_warn(iproc_i2c->device, "bus is busy\n");
690 return -EBUSY;
691 }
692
693 iproc_i2c->msg = msg;
694
695 /* format and load slave address into the TX FIFO */
696 addr = i2c_8bit_addr_from_msg(msg);
697 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
698
699 /*
700 * For a write transaction, load data into the TX FIFO. Only allow
701 * loading up to TX FIFO size - 1 bytes of data since the first byte
702 * has been used up by the slave address
703 */
704 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
705 if (!(msg->flags & I2C_M_RD)) {
706 for (i = 0; i < tx_bytes; i++) {
707 val = msg->buf[i];
708
709 /* mark the last byte */
710 if (i == msg->len - 1)
711 val |= BIT(M_TX_WR_STATUS_SHIFT);
712
713 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
714 }
715 iproc_i2c->tx_bytes = tx_bytes;
716 }
717
718 /* mark as incomplete before starting the transaction */
719 if (iproc_i2c->irq)
720 reinit_completion(&iproc_i2c->done);
721
722 iproc_i2c->xfer_is_done = 0;
723
724 /*
725 * Enable the "start busy" interrupt, which will be triggered after the
726 * transaction is done, i.e., the internal start_busy bit, transitions
727 * from 1 to 0.
728 */
729 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
730
731 /*
732 * If TX data size is larger than the TX FIFO, need to enable TX
733 * underrun interrupt, which will be triggerred when the TX FIFO is
734 * empty. When that happens we can then pump more data into the FIFO
735 */
736 if (!(msg->flags & I2C_M_RD) &&
737 msg->len > iproc_i2c->tx_bytes)
738 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
739
740 /*
741 * Now we can activate the transfer. For a read operation, specify the
742 * number of bytes to read
743 */
744 val = BIT(M_CMD_START_BUSY_SHIFT);
745 if (msg->flags & I2C_M_RD) {
746 iproc_i2c->rx_bytes = 0;
747 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
748 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
749 else
750 iproc_i2c->thld_bytes = msg->len;
751
752 /* set threshold value */
753 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
754 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
755 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
756 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
757
758 /* enable the RX threshold interrupt */
759 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
760
761 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
762 (msg->len << M_CMD_RD_CNT_SHIFT);
763 } else {
764 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
765 }
766
767 if (iproc_i2c->irq)
768 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
769
770 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
771 }
772
bcm_iproc_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg msgs[],int num)773 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
774 struct i2c_msg msgs[], int num)
775 {
776 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
777 int ret, i;
778
779 /* go through all messages */
780 for (i = 0; i < num; i++) {
781 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
782 if (ret) {
783 dev_dbg(iproc_i2c->device, "xfer failed\n");
784 return ret;
785 }
786 }
787
788 return num;
789 }
790
bcm_iproc_i2c_functionality(struct i2c_adapter * adap)791 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
792 {
793 u32 val;
794
795 /* We do not support the SMBUS Quick command */
796 val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
797
798 if (adap->algo->reg_slave)
799 val |= I2C_FUNC_SLAVE;
800
801 return val;
802 }
803
804 static struct i2c_algorithm bcm_iproc_algo = {
805 .master_xfer = bcm_iproc_i2c_xfer,
806 .functionality = bcm_iproc_i2c_functionality,
807 .reg_slave = bcm_iproc_i2c_reg_slave,
808 .unreg_slave = bcm_iproc_i2c_unreg_slave,
809 };
810
811 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
812 .max_read_len = M_RX_MAX_READ_LEN,
813 };
814
bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev * iproc_i2c)815 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
816 {
817 unsigned int bus_speed;
818 u32 val;
819 int ret = of_property_read_u32(iproc_i2c->device->of_node,
820 "clock-frequency", &bus_speed);
821 if (ret < 0) {
822 dev_info(iproc_i2c->device,
823 "unable to interpret clock-frequency DT property\n");
824 bus_speed = 100000;
825 }
826
827 if (bus_speed < 100000) {
828 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
829 bus_speed);
830 dev_err(iproc_i2c->device,
831 "valid speeds are 100khz and 400khz\n");
832 return -EINVAL;
833 } else if (bus_speed < 400000) {
834 bus_speed = 100000;
835 } else {
836 bus_speed = 400000;
837 }
838
839 iproc_i2c->bus_speed = bus_speed;
840 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
841 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
842 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
843 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
844
845 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
846
847 return 0;
848 }
849
bcm_iproc_i2c_probe(struct platform_device * pdev)850 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
851 {
852 int irq, ret = 0;
853 struct bcm_iproc_i2c_dev *iproc_i2c;
854 struct i2c_adapter *adap;
855 struct resource *res;
856
857 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
858 GFP_KERNEL);
859 if (!iproc_i2c)
860 return -ENOMEM;
861
862 platform_set_drvdata(pdev, iproc_i2c);
863 iproc_i2c->device = &pdev->dev;
864 iproc_i2c->type =
865 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
866 init_completion(&iproc_i2c->done);
867
868 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
869 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
870 if (IS_ERR(iproc_i2c->base))
871 return PTR_ERR(iproc_i2c->base);
872
873 if (iproc_i2c->type == IPROC_I2C_NIC) {
874 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
875 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
876 res);
877 if (IS_ERR(iproc_i2c->idm_base))
878 return PTR_ERR(iproc_i2c->idm_base);
879
880 ret = of_property_read_u32(iproc_i2c->device->of_node,
881 "brcm,ape-hsls-addr-mask",
882 &iproc_i2c->ape_addr_mask);
883 if (ret < 0) {
884 dev_err(iproc_i2c->device,
885 "'brcm,ape-hsls-addr-mask' missing\n");
886 return -EINVAL;
887 }
888
889 spin_lock_init(&iproc_i2c->idm_lock);
890
891 /* no slave support */
892 bcm_iproc_algo.reg_slave = NULL;
893 bcm_iproc_algo.unreg_slave = NULL;
894 }
895
896 ret = bcm_iproc_i2c_init(iproc_i2c);
897 if (ret)
898 return ret;
899
900 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
901 if (ret)
902 return ret;
903
904 irq = platform_get_irq(pdev, 0);
905 if (irq > 0) {
906 ret = devm_request_irq(iproc_i2c->device, irq,
907 bcm_iproc_i2c_isr, 0, pdev->name,
908 iproc_i2c);
909 if (ret < 0) {
910 dev_err(iproc_i2c->device,
911 "unable to request irq %i\n", irq);
912 return ret;
913 }
914
915 iproc_i2c->irq = irq;
916 } else {
917 dev_warn(iproc_i2c->device,
918 "no irq resource, falling back to poll mode\n");
919 }
920
921 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
922
923 adap = &iproc_i2c->adapter;
924 i2c_set_adapdata(adap, iproc_i2c);
925 snprintf(adap->name, sizeof(adap->name),
926 "Broadcom iProc (%s)",
927 of_node_full_name(iproc_i2c->device->of_node));
928 adap->algo = &bcm_iproc_algo;
929 adap->quirks = &bcm_iproc_i2c_quirks;
930 adap->dev.parent = &pdev->dev;
931 adap->dev.of_node = pdev->dev.of_node;
932
933 return i2c_add_adapter(adap);
934 }
935
bcm_iproc_i2c_remove(struct platform_device * pdev)936 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
937 {
938 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
939
940 if (iproc_i2c->irq) {
941 /*
942 * Make sure there's no pending interrupt when we remove the
943 * adapter
944 */
945 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
946 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
947 synchronize_irq(iproc_i2c->irq);
948 }
949
950 i2c_del_adapter(&iproc_i2c->adapter);
951 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
952
953 return 0;
954 }
955
956 #ifdef CONFIG_PM_SLEEP
957
bcm_iproc_i2c_suspend(struct device * dev)958 static int bcm_iproc_i2c_suspend(struct device *dev)
959 {
960 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
961
962 if (iproc_i2c->irq) {
963 /*
964 * Make sure there's no pending interrupt when we go into
965 * suspend
966 */
967 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
968 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
969 synchronize_irq(iproc_i2c->irq);
970 }
971
972 /* now disable the controller */
973 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
974
975 return 0;
976 }
977
bcm_iproc_i2c_resume(struct device * dev)978 static int bcm_iproc_i2c_resume(struct device *dev)
979 {
980 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
981 int ret;
982 u32 val;
983
984 /*
985 * Power domain could have been shut off completely in system deep
986 * sleep, so re-initialize the block here
987 */
988 ret = bcm_iproc_i2c_init(iproc_i2c);
989 if (ret)
990 return ret;
991
992 /* configure to the desired bus speed */
993 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
994 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
995 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
996 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
997
998 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
999
1000 return 0;
1001 }
1002
1003 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1004 .suspend_late = &bcm_iproc_i2c_suspend,
1005 .resume_early = &bcm_iproc_i2c_resume
1006 };
1007
1008 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1009 #else
1010 #define BCM_IPROC_I2C_PM_OPS NULL
1011 #endif /* CONFIG_PM_SLEEP */
1012
1013
bcm_iproc_i2c_reg_slave(struct i2c_client * slave)1014 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1015 {
1016 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1017
1018 if (iproc_i2c->slave)
1019 return -EBUSY;
1020
1021 if (slave->flags & I2C_CLIENT_TEN)
1022 return -EAFNOSUPPORT;
1023
1024 iproc_i2c->slave = slave;
1025 bcm_iproc_i2c_slave_init(iproc_i2c, false);
1026 return 0;
1027 }
1028
bcm_iproc_i2c_unreg_slave(struct i2c_client * slave)1029 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1030 {
1031 u32 tmp;
1032 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1033
1034 if (!iproc_i2c->slave)
1035 return -EINVAL;
1036
1037 iproc_i2c->slave = NULL;
1038
1039 /* disable all slave interrupts */
1040 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1041 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1042 IE_S_ALL_INTERRUPT_SHIFT);
1043 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1044
1045 /* Erase the slave address programmed */
1046 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1047 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1048 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1049
1050 return 0;
1051 }
1052
1053 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1054 {
1055 .compatible = "brcm,iproc-i2c",
1056 .data = (int *)IPROC_I2C,
1057 }, {
1058 .compatible = "brcm,iproc-nic-i2c",
1059 .data = (int *)IPROC_I2C_NIC,
1060 },
1061 { /* sentinel */ }
1062 };
1063 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1064
1065 static struct platform_driver bcm_iproc_i2c_driver = {
1066 .driver = {
1067 .name = "bcm-iproc-i2c",
1068 .of_match_table = bcm_iproc_i2c_of_match,
1069 .pm = BCM_IPROC_I2C_PM_OPS,
1070 },
1071 .probe = bcm_iproc_i2c_probe,
1072 .remove = bcm_iproc_i2c_remove,
1073 };
1074 module_platform_driver(bcm_iproc_i2c_driver);
1075
1076 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1077 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1078 MODULE_LICENSE("GPL v2");
1079
