Searched refs:SYSCTRL (Results 1 – 4 of 4) sorted by relevance
1 * Renesas R9A06G032 SYSCTRL7 - reg: Base address and length of the SYSCTRL IO block.21 - SYSCTRL node:34 - Other nodes can use the clocks provided by SYSCTRL as in:
57 - zte,tvenc-power-control: the phandle to SYSCTRL block followed by two58 integer cells. The first cell is the offset of SYSCTRL register used69 - zte,vga-power-control: the phandle to SYSCTRL block followed by two70 integer cells. The first cell is the offset of SYSCTRL register used
173 #define SYSCTRL 0x0464 macro294 rpi_touchscreen_write(ts, SYSCTRL, 0x040f); in rpi_touchscreen_enable()
76 #define SYSCTRL 0x0510 macro1196 ret = regmap_write(tc->regmap, SYSCTRL, value); in tc_stream_enable()1437 return reg != SYSCTRL; in tc_readable_reg()
