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Searched refs:STORE_RT_REG (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/drivers/net/ethernet/qlogic/qed/
Dqed_init_fw_funcs.c195 STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
222 STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0); in qed_enable_pf_rl()
228 STORE_RT_REG(p_hwfn, in qed_enable_pf_rl()
232 STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET, in qed_enable_pf_rl()
236 STORE_RT_REG(p_hwfn, in qed_enable_pf_rl()
238 STORE_RT_REG(p_hwfn, in qed_enable_pf_rl()
244 STORE_RT_REG(p_hwfn, in qed_enable_pf_rl()
253 STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0); in qed_enable_pf_wfq()
257 STORE_RT_REG(p_hwfn, in qed_enable_pf_wfq()
265 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET, in qed_enable_vport_rl()
[all …]
Dqed_cxt.c1408 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); in qed_cdu_init_common()
1421 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); in qed_cdu_init_common()
1433 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); in qed_cdu_init_common()
1484 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); in qed_cdu_init_pf()
1493 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); in qed_cdu_init_pf()
1536 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, in qed_cm_init_pf()
1547 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); in qed_dq_init_pf()
1550 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); in qed_dq_init_pf()
1553 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); in qed_dq_init_pf()
1556 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); in qed_dq_init_pf()
[all …]
Dqed_init_ops.h103 #define STORE_RT_REG(hwfn, offset, val) \ macro
Dqed_dev.c2591 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); in qed_init_cache_line_size()
2593 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); in qed_init_cache_line_size()
2594 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); in qed_init_cache_line_size()
2814 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0); in qed_hw_init_port()
2854 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); in qed_hw_init_pf()
2855 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, in qed_hw_init_pf()
2860 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, in qed_hw_init_pf()
2868 STORE_RT_REG(p_hwfn, in qed_hw_init_pf()
2873 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, in qed_hw_init_pf()
2875 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, in qed_hw_init_pf()
[all …]
Dqed_int.c1489 STORE_RT_REG(p_hwfn, in qed_int_cau_conf_pi()
2257 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); in qed_int_igu_init_rt()
Dqed_sriov.c834 STORE_RT_REG(p_hwfn, IGU_REG_VF_CONFIGURATION_RT_OFFSET, igu_vf_conf); in qed_iov_enable_vf_access()