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Searched refs:SR (Results 1 – 25 of 111) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.h31 SR(LVTMA_PWRSEQ_CNTL), \
32 SR(LVTMA_PWRSEQ_STATE)
49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
86 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
87 SR(DCFEV_CLOCK_CONTROL), \
96 SR(BLNDV_CONTROL),\
134 SR(DCHUB_FB_LOCATION),\
135 SR(DCHUB_AGP_BASE),\
136 SR(DCHUB_AGP_BOT),\
137 SR(DCHUB_AGP_TOP), \
[all …]
Ddce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
[all …]
Ddce_abm.h33 SR(BL_PWM_PERIOD_CNTL), \
34 SR(BL_PWM_CNTL), \
35 SR(BL_PWM_CNTL2), \
36 SR(BL_PWM_GRP1_REG_LOCK), \
37 SR(LVTMA_PWRSEQ_REF_DIV), \
38 SR(MASTER_COMM_CNTL_REG), \
39 SR(MASTER_COMM_CMD_REG), \
40 SR(MASTER_COMM_DATA_REG1)
44 SR(DC_ABM1_HG_SAMPLE_RATE), \
45 SR(DC_ABM1_LS_SAMPLE_RATE), \
[all …]
Ddce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
Ddce_link_encoder.h47 SR(DMCU_RAM_ACCESS_CTRL), \
48 SR(DMCU_IRAM_RD_CTRL), \
49 SR(DMCU_IRAM_RD_DATA), \
50 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
76 SR(DCI_MEM_PWR_STATUS)
86 SR(DCI_MEM_PWR_STATUS)
93 SR(DCI_MEM_PWR_STATUS)
99 SR(DCI_MEM_PWR_STATUS)
Ddce_i2c_hw.h88 SR(DC_I2C_ARBITRATION),\
89 SR(DC_I2C_CONTROL),\
90 SR(DC_I2C_SW_STATUS),\
91 SR(DC_I2C_TRANSACTION0),\
92 SR(DC_I2C_TRANSACTION1),\
93 SR(DC_I2C_TRANSACTION2),\
94 SR(DC_I2C_TRANSACTION3),\
95 SR(DC_I2C_DATA),\
96 SR(MICROSECOND_TIME_BASE_DIV)
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.h31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
36 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
39 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
40 SR(DCHVM_CTRL0), \
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubbub.h34 SR(DCHUBBUB_CRC_CTRL), \
35 SR(DCN_VM_FB_LOCATION_BASE),\
36 SR(DCN_VM_FB_LOCATION_TOP),\
37 SR(DCN_VM_FB_OFFSET),\
38 SR(DCN_VM_AGP_BOT),\
39 SR(DCN_VM_AGP_TOP),\
40 SR(DCN_VM_AGP_BASE)
47 SR(DCHUBBUB_CRC_CTRL), \
48 SR(DCN_VM_FB_LOCATION_BASE),\
49 SR(DCN_VM_FB_LOCATION_TOP),\
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubbub.h36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
37 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
44 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
45 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
[all …]
/Linux-v5.4/Documentation/networking/
Dseg6-sysctl.txt4 Accept or drop SR-enabled IPv6 packets on this interface.
12 Define HMAC policy for ingress SR-enabled packets on this interface.
15 0 - Accept SR packets without HMAC, validate SR packets with HMAC
16 1 - Drop SR packets without HMAC, validate SR packets with HMAC
/Linux-v5.4/Documentation/PCI/
Dpci-iov-howto.rst15 What is SR-IOV
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
37 Multiple methods are available for SR-IOV enablement.
39 enabling and disabling of the capability via API provided by SR-IOV core.
40 If the hardware has SR-IOV capability, loading its PF driver would
63 SR-IOV API
66 To enable SR-IOV capability:
79 To disable SR-IOV capability:
91 command below before enabling SR-IOV capabilities. This is the
[all …]
/Linux-v5.4/drivers/macintosh/
Dvia-cuda.c47 #define SR (10*RS) /* Shift register */ macro
346 (void)in_8(&via[SR]); in sync_egret()
361 (void)in_8(&via[SR]); in sync_egret()
389 (void)in_8(&via[SR]); /* clear any left-over data */ in cuda_init_via()
398 (void)in_8(&via[SR]); in cuda_init_via()
409 (void)in_8(&via[SR]); in cuda_init_via()
418 (void)in_8(&via[SR]); in cuda_init_via()
546 out_8(&via[SR], current_req->data[data_index++]); in cuda_start()
599 (void)in_8(&via[SR]); in cuda_interrupt()
609 (void)in_8(&via[SR]); in cuda_interrupt()
[all …]
Dvia-macii.c53 #define SR (10*RS) /* Shift register */ macro
174 x = via[SR]; in macii_init_via()
343 via[SR] = req->data[1]; in macii_start()
397 x = via[SR]; in macii_interrupt()
439 x = via[SR]; in macii_interrupt()
444 via[SR] = req->data[data_index++]; in macii_interrupt()
457 x = via[SR]; in macii_interrupt()
498 x = via[SR]; in macii_interrupt()
/Linux-v5.4/arch/alpha/math-emu/
Dmath.c104 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in alpha_fp_emul()
138 FP_SUB_S(SR, SA, SB); in alpha_fp_emul()
142 FP_ADD_S(SR, SA, SB); in alpha_fp_emul()
146 FP_MUL_S(SR, SA, SB); in alpha_fp_emul()
150 FP_DIV_S(SR, SA, SB); in alpha_fp_emul()
154 FP_SQRT_S(SR, SB); in alpha_fp_emul()
224 FP_CONV(S,D,1,1,SR,DB); in alpha_fp_emul()
262 FP_FROM_INT_S(SR, ((long)vb), 64, long); in alpha_fp_emul()
274 FP_PACK_SP(&vc, SR); in alpha_fp_emul()
/Linux-v5.4/arch/sparc/math-emu/
Dmath_32.c286 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_one_mathemu()
428 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_one_mathemu()
432 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_one_mathemu()
436 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_one_mathemu()
444 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_one_mathemu()
448 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_one_mathemu()
460 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
467 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; in do_one_mathemu()
468 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; in do_one_mathemu()
507 case 5: FP_PACK_SP (rd, SR); break; in do_one_mathemu()
Dmath_64.c181 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_mathemu()
433 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_mathemu()
437 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_mathemu()
441 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_mathemu()
449 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_mathemu()
453 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_mathemu()
471 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
474 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
481 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; in do_mathemu()
482 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; in do_mathemu()
[all …]
/Linux-v5.4/Documentation/sh/
Dregister-banks.txt8 bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
11 SR.RB banking
15 r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
17 when in the context of another bank. The developer must keep the SR.RB value
30 - The SR.IMASK interrupt handler makes use of this to set the
/Linux-v5.4/arch/sh/kernel/
Dhead_64.S157 getcon SR, r29
159 putcon r20, SR
246 getcon SR, r21
289 getcon SR, r21
292 putcon r22, SR /* Try to enable */
293 getcon SR, r22
/Linux-v5.4/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.c282 #define SR(reg) \ macro
293 SR(IRQENABLE); in dispc_save_context()
294 SR(CONTROL); in dispc_save_context()
295 SR(CONFIG); in dispc_save_context()
296 SR(LINE_NUMBER); in dispc_save_context()
299 SR(GLOBAL_ALPHA); in dispc_save_context()
301 SR(CONTROL2); in dispc_save_context()
302 SR(CONFIG2); in dispc_save_context()
305 SR(CONTROL3); in dispc_save_context()
306 SR(CONFIG3); in dispc_save_context()
[all …]
/Linux-v5.4/drivers/gpu/drm/omapdrm/dss/
Ddispc.c426 #define SR(dispc, reg) \ macro
437 SR(dispc, IRQENABLE); in dispc_save_context()
438 SR(dispc, CONTROL); in dispc_save_context()
439 SR(dispc, CONFIG); in dispc_save_context()
440 SR(dispc, LINE_NUMBER); in dispc_save_context()
443 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
445 SR(dispc, CONTROL2); in dispc_save_context()
446 SR(dispc, CONFIG2); in dispc_save_context()
449 SR(dispc, CONTROL3); in dispc_save_context()
450 SR(dispc, CONFIG3); in dispc_save_context()
[all …]
/Linux-v5.4/drivers/media/pci/ngene/
Dngene-core.c79 while (Cur->ngeneBuffer.SR.Flags & 0x80) { in demux_tasklet()
82 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
88 Cur->ngeneBuffer.SR. in demux_tasklet()
102 Cur->ngeneBuffer.SR.Flags &= in demux_tasklet()
115 Cur->ngeneBuffer.SR.Flags &= ~0x40; in demux_tasklet()
122 Cur->ngeneBuffer.SR.DTOUpdate = in demux_tasklet()
131 if (Cur->ngeneBuffer.SR.Flags & 0x01) in demux_tasklet()
133 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
139 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
144 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
[all …]
/Linux-v5.4/arch/sh/include/cpu-sh5/cpu/
Dregisters.h22 #define SR cr0 macro
84 #define __SR __str(SR)
/Linux-v5.4/Documentation/networking/device_drivers/intel/
Dixgbe.rst51 | SR Modules |
53 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | FTLX8571D3BCV-IT |
55 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | AFBR-703SDZ-IN2 |
57 | Intel | DUAL RATE 1G/10G SFP+ SR (bailed) | AFBR-703SDDZ-IN1 |
74 | Finisar | SFP+ SR bailed, 10g single rate | FTLX8571D3BCL |
76 | Avago | SFP+ SR bailed, 10g single rate | AFBR-700SDZ |
80 | Finisar | DUAL RATE 1G/10G SFP+ SR (No Bail) | FTLX8571D3QCV-IT |
82 | Avago | DUAL RATE 1G/10G SFP+ SR (No Bail) | AFBR-703SDZ-IN1 |
135 SR Dual Port Express Module only supports SR optical modules). If you plug in
139 - LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
[all …]
/Linux-v5.4/arch/sh/kernel/cpu/sh2a/
Dentry.S46 bld.b #6,@(0,r2) !previus SR.MD
47 bst.b #6,@(4*4,r15) !set cpu mode to SR.MD
50 bset.b #6,@(0,r2) !set SR.MD
63 mov.l r0,@-r15 ! original SR
91 mov.l @r8+,r11 ! old SR
/Linux-v5.4/drivers/staging/unisys/Documentation/ABI/
Dsysfs-platform-visorchipset59 responsible for enabling and disabling SR-IOV devices when the
62 Some SR-IOV devices have problems when the PF is reset without
78 responsible for enabling and disabling SR-IOV devices when the
81 Some SR-IOV devices have problems when the PF is reset without

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